FIDIV instruction (x87)

FIDIV divides ST(0) by a signed integer from memory, a word (DE /6) or a doubleword (DA /6), and leaves the quotient in ST(0). There is no 64-bit form, although FILD loads quadwords. The integer becomes an 80-bit value exactly, so FIDIV rounds once, like FDIV with a memory operand, whose page covers the precision control and the rounding. FIDIVR divides the other way round, the integer by ST(0).

Not an integer division

Only the divisor is an integer; the arithmetic is the x87’s, with its exceptions and none of DIV’s:

Dividing by an integer 0 raises ZE, not #DE, and with ZE masked gives an infinity of the quotient’s sign. A zero ST(0) over 0 is an invalid operation instead: Zen 5 gave the QNaN indefinite with IE, for +0 and -0 alike.
The quotient keeps its fraction and can underflow: Zen 5 turned a denormal over 12345 into +0, with DE, UE and PE.
Infinity over an integer stays infinite, with no exception: Zen 5 divided +infinity by -32768 into -infinity.
A QNaN in ST(0) passes through unchanged; an SNaN raises IE and comes out quieted. An empty ST(0) is a stack underflow, with IE, SF and C1 = 0.

Compilers

For x / n with a long double x and an int n, Clang 23 at -O2 loads x, stores n to the stack if it came in a register, and emits fidiv dword ptr; a short gets the word form. GCC 14 never uses it: it loads n with FILD and x with FLD, then divides with FDIVRP. Both give the same bits, since the conversion is exact. With -m32 -march=i386 on doubles, Clang still uses FIDIV, while GCC loads n with FILD and divides the double in memory by it with FDIVR.

AMD’s Zen 5 guide lists FIDIV and FIDIVR as two macro-ops on pipe FP1, where FDIV is one.

Forms

Every encoding of FIDIV that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FIDIV m32int` FIDIV_ST0_MEMmem32int	`DA /6`	FPU
`FIDIV m16int` FIDIV_ST0_MEMmem16int	`DE /6`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(st0):
    underflow()                  # IE, SF, C1 = 0
    st0 = INDEFINITE
else:
    st0 = div(st0, signed(src))  # by zero: ZE and an infinity
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 18 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FIDIV m16int` `FIDIV m32int`
`m16/32int`	explicit	read
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Not an integer division#

Compilers#