FIDIVR instruction (x87)

Forms

Every encoding of FIDIVR that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FIDIVR m32int` FIDIVR_ST0_MEMmem32int	`DA /7`	FPU
`FIDIVR m16int` FIDIVR_ST0_MEMmem16int	`DE /7`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(st0):
    underflow()                  # IE, SF, C1 = 0
    st0 = INDEFINITE
else:
    st0 = div(signed(src), st0)  # the integer over ST(0)
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FIDIVR m16int` `FIDIVR m32int`
`m16/32int`	explicit	read
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions