FILD instruction (x87)

FILD reads a signed 16-, 32- or 64-bit integer from memory, converts it to the 80-bit format and pushes it onto the x87 stack. The conversion is always exact: the format’s 64-bit significand holds every 64-bit integer, so neither PC nor RC plays a part, and no exception is possible but a stack overflow. FILD has no register form, so compilers store a general-purpose register first: GCC 14 and Clang 23 at -O2 compile (long double)i for an int i to a MOV of EDI to the stack and fild DWORD PTR, and for a long to the QWORD versions.

64-bit integers in 32-bit code

SSE2’s CVTSI2SD takes a 64-bit integer only in 64-bit mode, so 32-bit code converts a long long with FILD m64int even when its arithmetic uses SSE2. With -m32 and SSE2 math, both compilers load the argument with fild QWORD PTR; GCC returns that result as it is, and Clang rounds it to a double first, storing it with FSTP m64fp and loading it back. The way back is FISTP m64int.

Unsigned sources

FILD reads only signed integers. For a uint64_t with its top bit set it loads a value 2^64 too small, so compilers add 2^64 when the sign bit is set: GCC 14 tests the register and branches to an FADD of 2^64, stored as a single constant; Clang 23 picks either 0 or 2^64 from a two-entry table by the sign, without a branch, and always adds. A 32-bit unsigned value needs nothing of the kind: compilers zero-extend it and use the 64-bit form.

AMD’s Zen 5 guide lists FILD as one macro-op. FIADD, FIMUL and the other integer arithmetic take an integer operand from memory directly, converting it the same way.

Forms

Every encoding of FILD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FILD m32int` FILD_ST0_MEMmem32int	`DB /0`	FPU
`FILD m16int` FILD_ST0_MEMmem16int	`DF /0`	FPU
`FILD m64int` FILD_ST0_MEMm64int	`DF /5`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not empty(st7):                   # the register the push fills
    overflow()
    push(INDEFINITE)
else:
    push(to_f80(signed(src)))        # exact at every width, whatever
    c1 = 0                           # PC says
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 45 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FILD m16int` `FILD m32int` `FILD m64int`
`m16/32/64int`	explicit	read
`x87 register stack`	implicit	push
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

64-bit integers in 32-bit code#

Unsigned sources#