FINCSTP instruction (x87)

FINCSTP adds 1 to TOP, the 3-bit field of the x87 status word that says which physical register is ST(0); from 7 it wraps to 0. Nothing else changes: every register keeps its value and its tag, so the old ST(0) becomes ST(7), ST(1) becomes ST(0), and so on around the ring of eight. It is two bytes, D9 F7. FDECSTP turns the ring the other way.

Half a pop

A pop, the last step of FSTP, FADDP and their kin, tags ST(0) empty and then adds 1 to TOP. FINCSTP does only the second half. On Zen 5, after FINCSTP on a stack of three values, the old ST(0) sat in ST(7), still tagged valid. The next push, an FLD for one, needs ST(7) empty, so it would find a stack overflow there, with the QNaN indefinite pushed if IE is masked. To drop ST(0) without storing it:

fstp st(0) stores ST(0) onto itself and pops, the idiom GCC 14 and Clang 23 use; on an empty ST(0) it is a stack underflow;
FFREE ST(0) followed by FINCSTP never reads the value, so it works on an empty register too.

No exception of its own

FINCSTP looks at no register, so an empty or a full stack is no error for it: Zen 5 moved TOP from 7 to 0 with all eight registers empty, and from 3 to 4 with all eight full, and raised nothing. It is still a waiting instruction: Intel’s manual lists #MF for a pending unmasked exception. Both manuals clear C1 and leave C0, C2 and C3 undefined; in all six of Zen 5’s cases FINCSTP cleared C1 and kept the other three.

AMD’s Zen 5 guide lists FINCSTP, like FDECSTP and FFREE, as one macro-op, six per cycle, with no FP pipe named.

Forms

Every encoding of FINCSTP that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FINCSTP` FINCSTP	`D9 F7`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

top = top + 1                        # the tags stay: no register is
c1 = 0                               # freed, as a pop would
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FINCSTP`
`x87 status word`	implicit	read, write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Half a pop#

No exception of its own#