FIST instruction (x87)

FIST converts ST(0) to a signed 16- or 32-bit integer and stores it, leaving the register stack as it was. FISTP does the same and pops, and only FISTP has a 64-bit form. Both round as RC says, to nearest even unless code changes it, and both store the integer indefinite when the value does not fit; FISTP’s page covers casts, which truncate, and the out-of-range rules.

When the value stays

Compilers emit FIST where ST(0) is still needed after the store. With -fno-math-errno, GCC 14 at -O2 compiles *a = __builtin_irintl(x); *b = x; on a long double to FLD of x, fist DWORD PTR [rdi] and fstp TBYTE PTR [rsi]. A 64-bit long from lrintl cannot use it: in the same code GCC and Clang 23 copy the register with fld st(0) and store the copy with fistp QWORD PTR. In 32-bit code, where long has 32 bits, both use fist DWORD PTR there.

Rounding and C1

Zen 5 stored 2 for 2.5 and -2 for -2.5 under rounding to nearest, and 0 for -0.5, since an integer has no -0. Each of these set PE. C1 says whether the magnitude was rounded up: 1.5 to 2 and -1.5 to -2 set it, 2.5 to 2 left it clear, and so did -0.5 to 0.

The ends of the range

Whether a value fits is decided after rounding, so RC matters at the edges. 2147483647.5 rounds to 2^31 under rounding to nearest, which does not fit, and gave the indefinite 80000000H with IE; toward zero it gave 2147483647. -2147483648.5 went the other way: -2147483648 with PE to nearest, the indefinite with IE when rounding down. The 16-bit form did the same with 32767.5 and -32768.5.

With IE masked, an empty ST(0) also stores the indefinite, with SF set. With IE unmasked, nothing is stored. An unmasked PE does not stop the store: Zen 5 stored 2 for 2.5, and the #MF came at the FWAIT that the probe runs after each x87 case.

AMD’s Zen 5 guide lists FIST as two macro-ops, one per cycle.

Forms

Every encoding of FIST that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FIST m32int` FIST_MEMmem32int_ST0	`DB /2`	FPU
`FIST m16int` FIST_MEMmem16int_ST0	`DF /2`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(st0):
    underflow()
    v = INDEFINITE
else:
    v = st0
r = cvt_int(v, dest.bits)            # rounded by RC; a NaN, an
                                     # infinity or a number out of
                                     # range gives the integer
                                     # indefinite, with IE
dest.write(r)
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 64 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FIST m16int` `FIST m32int`
`m16/32int`	explicit	write
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

When the value stays#

Rounding and C1#

The ends of the range#