FISTP instruction (x87)

FISTP converts ST(0) to a signed 16-, 32- or 64-bit integer, stores it and pops. The conversion rounds as RC says, which is to nearest even unless code changes it, so 2.5 becomes 2 and -1.5 becomes -2. FIST stores without popping and has no 64-bit form; only FISTP writes a 64-bit integer.

Casts and the control word

C’s casts truncate, so compilers change RC around the store. GCC 14 and Clang 23 at -O2 compile (long)x on a long double to

fnstcw of the control word to the stack, and a copy with or ah, 12 (Clang: or eax, 3072), which sets RC to toward zero,
FLDCW of the copy, fistp QWORD PTR, and FLDCW of the saved word to restore it.

Intel’s optimization manual counts these changes of the control word as the cost of x87 conversions (Section 3.9.3.1). With -msse3, both compilers emit FISTTP instead, which truncates whatever RC says and needs no FLDCW. lrintl(x), which rounds by the current mode, becomes a bare fistp once -fno-math-errno lets them inline it. In 32-bit code, (long long)d uses this sequence even when the arithmetic uses SSE2, which has no 64-bit integer conversion there.

Out of range

A NaN, an infinity, or a value whose rounded integer does not fit gives the integer indefinite, the most negative integer of the size (8000H, 80000000H or 8000000000000000H), with IE set: Zen 5 stored 8000H for 32768.0 into 16 bits. With IE unmasked, nothing is stored and nothing popped. So a 16-bit FISTP is no unsigned-short conversion: values from 32768 up do not fit.

For (unsigned long)x both compilers compare x with 2^63, subtract 2^63 from larger values before the FISTP and flip bit 63 of the result afterwards.

AMD’s Zen 5 guide lists FISTP to memory, like FISTTP, as two macro-ops.

Forms

Every encoding of FISTP that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FISTP m32int` FISTP_MEMmem32int_ST0	`DB /3`	FPU
`FISTP m16int` FISTP_MEMmem16int_ST0	`DF /3`	FPU
`FISTP m64int` FISTP_MEMm64int_ST0	`DF /7`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(st0):
    underflow()
    v = INDEFINITE
else:
    v = st0
r = cvt_int(v, dest.bits)            # rounded by RC; a NaN, an
                                     # infinity or a number out of
                                     # range gives the integer
                                     # indefinite, with IE
dest.write(r)
pop()
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 45 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FISTP m16int` `FISTP m32int` `FISTP m64int`
`m16/32/64int`	explicit	write
`x87 register stack`	implicit	pop
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Casts and the control word#

Out of range#