FLD

FLD pushes a value onto the x87 register stack: TOP moves down by one, and the new ST(0) receives a single, a double or an 80-bit extended value from memory, or a copy of another register. Nearly every x87 computation begins with it. In 64-bit code that means long double, which the System V ABI passes in memory and returns in ST(0): GCC 14 at -O2 compiles a + b on two of them to fld TBYTE PTR [rsp+8], fld TBYTE PTR [rsp+24] and faddp st(1), st, which leaves the sum in ST(0) for the caller; Clang 23 loads them in the other order. In 32-bit code, float and double results come back in ST(0) too.

Loads widen exactly#

Every single and every double fits the 80-bit format exactly, so FLD m32fp and m64fp never round, and PC plays no part. A denormal source becomes a normal 80-bit number and raises DE; a signaling NaN arrives quiet and raises IE. FLD m80fp and FLD ST(i) copy their source bit for bit, whatever its class, with neither exception.

Copying a register#

FLD ST(i) names the register as it was before the push, so FLD ST(0) duplicates the top of the stack. Compilers use it to keep a value that the next instruction consumes: for (x * x + 3) * x both emit fld st(0), fmul st, st(1), an FADD of the constant 3 stored as a single, and fmulp st(1), st.

A full stack#

The stack has eight registers. If ST(7), the one the push would fill, is not empty, FLD is a stack overflow: IE and SF are set, C1 is set to 1, and with IE masked the value pushed is the QNaN indefinite. So values left behind turn later loads into NaNs, and so does MMX code, which marks every x87 register as in use: Intel’s optimization manual asks for EMMS before x87 code follows (Section 6.2). FLD ST(i) of an empty register is a stack underflow instead, checked first.

Intel’s manual says that an unmasked denormal-operand exception leaves TOP and the registers unchanged. Zen 5 differs for FLD: with DE unmasked, a denormal single or double was still pushed, normalized, and #MF came at the next waiting instruction.

AMD’s Zen 5 guide lists FLD as one macro-op that either of two pipes runs. FILD loads integers, FBLD packed BCD, and FLD1, FLDZ and their kin push constants; FSTP is the store that pops.

In the optimization guide

What the optimization guide says about FLD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Silvermont to Goldmont Plus

• Front end: On Silvermont these instructions come from the microcode ROM; Goldmont decodes them directly, except an indirect call through memory.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not empty(st7):               # the register the push fills
    overflow()
    push(INDEFINITE)
else:
    push(to_f80(src))            # exact; an SNaN comes quiet, with
    c1 = 0                       # IE; a denormal raises DE, and Zen 5
                                 # pushes it even with DE unmasked
c0 = c2 = c3 = UNDEFINED

if not src.is_memory and empty(src):
    underflow()                  # before a full stack: the
    push(INDEFINITE)             # indefinite overwrites ST(7)
elif not empty(st7):
    overflow()
    push(INDEFINITE)
else:
    push(src)                    # as it is, of any class: no IE for
    c1 = 0                       # an SNaN, no DE for a denormal
c0 = c2 = c3 = UNDEFINED

Operands

Flags

Attributes

What else XED records about the forms. How to read.

All forms

may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More x87 instructions

• FCOS
• FDECSTP
• FDIV
• FDIVP
• FDIVR
• FDIVRP
• FFREE
• FFREEP
• FIADD
• FICOM
• FICOMP
• FIDIV
• FIDIVR
• FILD
• FIMUL
• FINCSTP
• FIST
• FISTP
• FISUB
• FISUBR
• FLD1
• FLDCW
• FLDENV
• FLDL2E
• FLDL2T
• FLDLG2
• FLDLN2
• FLDPI
• FLDZ
• FMUL
• FMULP
• FNCLEX
• FNDISI
• FNENI
• FNINIT
• FNOP
• FNSAVE
• FNSETPM
• FNSTCW
• FNSTENV

All 90 x87 instructions