FLD1 instruction (x87)

FLD1 pushes +1.0 onto the x87 register stack. It is two bytes, D9 E8, with no memory operand, so it is the cheapest way to get a 1 into an x87 register. Six siblings push other constants: FLDZ +0, FLDPI pi, FLDL2E log2(e), FLDL2T log2(10), FLDLG2 log10(2) and FLDLN2 ln(2).

Exact, unlike its siblings

+1 and +0 are exact in any format, so FLD1 and FLDZ give the same bits whatever the control word says. The other five come from internal constants of 66 bits rounded to 64 by RC; Intel’s manual says that this rounding raises no PE and leaves C1 clear, and that rounding to nearest gives the 8087’s values. FLD1 itself clears C1.

Where compilers use it

GCC 14 and Clang 23 at -O2 load a long double 1 with FLD1 rather than from memory:

x + 1.0L becomes fld of x, fld1 and faddp st(1), st;
1.0L / x becomes fld of x, fld1 and fdivrp st(1), st;
with -ffast-math, GCC’s log2l(x) is fld1, fld of x and FYL2X, which computes 1 * log2(x), and its atanl(x) is FPATAN of the point (1, x).

In 32-bit code, where doubles live on the x87 stack too, both compilers with -m32 -march=i386 return a constant 1.0 with FLD1 as well.

A full stack

FLD1 is a push like FLD: ST(7) must be empty. Otherwise it is a stack overflow, with IE and SF set and C1 = 1; with IE masked TOP still moves and the QNaN indefinite is pushed in place of the 1. With IE unmasked Zen 5 changed no register, and #MF came at the next waiting instruction.

AMD’s Zen 5 guide lists FLD1 and its six siblings as one macro-op each, on one FP pipe.

Forms

Every encoding of FLD1 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FLD1` FLD1	`D9 E8`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not empty(st7):
    overflow()
    push(INDEFINITE)
else:
    push(to_f80(1))
    c1 = 0
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 8 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FLD1`
`ST(0)`	implicit	write
`x87 register stack`	implicit	push
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Exact, unlike its siblings#

Where compilers use it#

A full stack#