FLDCW instruction (x87)

FLDCW loads the x87 control word from 16 bits of memory. The word holds the six exception masks (bits 0 to 5, a set bit masks), the precision control PC (bits 9:8: 00 for 24 bits of significand, 10 for 53, 11 for 64) and the rounding control RC (bits 11:10: 00 to nearest, 01 down, 10 up, 11 toward zero). Bit 12, the infinity control of the 80287, is kept but has no effect. FNINIT sets the word to 037FH: every exception masked, 64 bits, to nearest. Reading it back with FNSTCW shows bit 6 as 1 and bits 7 and 15:13 as 0, whatever was loaded.

Where compilers use it

The x87 has no truncating conversion before SSE3, so a C cast of a float to an integer saves the control word with FNSTCW, sets RC to 11 in a copy, loads it with FLDCW, converts with FISTP and loads the saved word back: GCC 14 and Clang 23 at -O2 emit that for (int)x on a long double, two FLDCWs per cast. The calling conventions make the control word callee-saved (System V, i386), so a function that changes it restores it.

Unmasking a pending flag

Unmasking an exception whose flag is already set in the status word does not fault at FLDCW: the next waiting x87 instruction raises #MF. Code that unmasks exceptions therefore clears the flags first with FNCLEX.

Cost

Intel’s optimization manual calls FLDCW potentially expensive. Recent Intel processors make it cheap when code alternates between two values that differ only in PC, RC and bit 12; a change of the masks, or a cycle through three or more values, is slow, and the manual advises storing and reloading the word as 16-bit operations so the load can take the stored data directly (Sections 3.9.3 and 3.9.3.1). AMD’s Zen 5 guide lists FLDCW as microcoded. SSE3’s FISTTP, and SSE2’s CVTTSD2SI for doubles, avoid the change of mode altogether.

Forms

Every encoding of FLDCW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FLDCW m16` FLDCW_MEMmem16	`D9 /5`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

fcw = src & 0x1F3F | 0x0040          # bits 15:13 and 7 read 0, bit 6 1
c0 = c1 = c2 = c3 = UNDEFINED
# a flag the new masks unmask raises #MF at the next waiting
# instruction; one pending before raises it at FLDCW, which waits

Run on AMD Zen 5 (EPYC 9645): 15 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FLDCW m16`
`m16`	explicit	read
`x87 control word`	implicit	write
`x87 status word`	implicit	write

Flags

U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	U	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Where compilers use it#

Unmasking a pending flag#

Cost#