FLDENV instruction (x87)

FLDENV loads the x87 environment from memory: the control, status and tag words, the last instruction pointer with its opcode and the last data pointer, everything but the eight data registers. It reads what FNSTENV stores: 28 bytes with a 32- or 64-bit operand size, 14 with the 66 prefix, whose image has 16-bit pointers and no opcode. FRSTOR loads the same environment followed by the registers.

What it takes as stored

FLDENV treats the image as FRSTOR does, and FRSTOR’s page has the details: the tag word only says which registers are empty, ES and B follow the loaded flags and masks, and the control word keeps its defined bits. Zen 5 turned an image with a control word of FFFFH into 1F7FH, a tag word of 0, all valid, into 00A0H, two registers tagged special for what they held, and ignored bits 31:16 of the control, status and tag doublewords of the 28-byte image.

FLDENV is a waiting instruction: with an unmasked exception pending before it, Zen 5 raised #MF and loaded nothing.

Flags it makes pending

An image whose status word holds a flag that its control word unmasks makes that exception pending: Zen 5 loaded ZE with ZE unmasked, set ES and B, and #MF came at the next waiting x87 instruction. Code that loads an environment saved while an exception was pending gets that exception again unless it clears the flag in the image first, as Intel’s manual suggests.

In compiled code

GCC 14 at -O2 restores the environment with FLDENV at the end of a C11 atomic compound assignment on floats, after the LOCK CMPXCHG loop that FNSTENV’s page describes. Right before it comes fnstsw ax: the reload puts back the flags of the time before the loop, so the status word is read first, and the flags of the attempt that succeeded are ORed with MXCSR’s and passed to __atomic_feraiseexcept, which raises them again. Clang 23 emits only the loop. AMD’s Zen 5 guide lists FLDENV as microcoded.

Forms

Every encoding of FLDENV that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FLDENV m14byte` FLDENV_MEMmem14	`66 D9 /4`	FPU
`FLDENV m28byte` FLDENV_MEMmem28	`REX.W D9 /4` `D9 /4`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

FLDENV m28byte

a = src.address                  # bits 31:16 of the words ignored
fcw = load(a, 16) & 0x1F3F | 0x40   # bits 15:13 and 7 read as 0,
                                 # bit 6 as 1
fsw = load(a + 4, 16)            # TOP, the codes and the flags;
                                 # ES and B follow the flags and
                                 # the masks, whatever it holds
ftw = load(a + 8, 16)            # only which registers are empty:
                                 # the other tags come from what
                                 # the registers hold
fip = load(a + 12, 32)
fcs = load(a + 16, 16)
fop = load(a + 18, 16) & 0x7FF
fdp = load(a + 20, 32)
fds = load(a + 24, 16)
# a flag it sets whose mask it clears is pending: the next
# waiting x87 instruction raises #MF

Run on AMD Zen 5 (EPYC 9645): 6 cases.

FLDENV m14byte

a = src.address
fcw = load(a, 16) & 0x1F3F | 0x40
fsw = load(a + 2, 16)            # ES and B follow the flags
ftw = load(a + 4, 16)            # only which are empty
fip = load(a + 6, 16)            # zero-extended
fcs = load(a + 8, 16)
fop = 0                          # the 14 bytes have no opcode
fdp = load(a + 10, 16)
fds = load(a + 12, 16)

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FLDENV m14byte` `FLDENV m28byte`
`m14/28byte`	explicit	read
`x87 status word`	implicit	write

Flags

M modified; blank: not affected. How to read.

C0	C1	C2	C3
All forms
M	M	M	M

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

What it takes as stored#

Flags it makes pending#

In compiled code#