FLDL2E instruction (x87)

FLDL2E pushes log2(e), about 1.4427, onto the x87 register stack. It is two bytes, D9 EA, and one of the seven constant loads that FLD1’s page describes together. The x87 computes powers and logarithms in base 2, and this constant is the factor that turns base e into base 2: e^x = 2^(x * log2(e)).

Its job in exp

F2XM1 and FSCALE only raise 2 to a power, so an exponential of e starts with FLDL2E. With -ffast-math, GCC 14 at -O2 compiles expl(x) on a long double to FLD of x, fldl2e and fmulp, then the base-2 sequence of F2XM1’s page; its expm1l begins the same way, and exp10l loads FLDL2T, log2(10), instead. The natural logarithm goes the other way with another constant: logl(x) is FLDLN2, FLD of x and FYL2X, which computes ln(2) * log2(x). Without -ffast-math, and with Clang 23 in either case, these are calls of the library.

The product x * log2(e) is rounded to 64 bits before the exponent is split off, so its rounding error becomes an error in the power of 2 that grows with |x|: for a product near 2^14, half an ulp is 2^-50, and the result keeps only about 50 of its 64 bits.

Rounding of the constant

Zen 5 gave 3FFF B8AA3B29 5C17F0BC when rounding to nearest or up, about 0.26 ulp above log2(e), and …F0BB, about 0.74 ulp below, when rounding down or toward zero, without PE and with C1 cleared. PC at 24 or 53 bits did not shorten it. GCC 14 also returns a long double constant equal to log2(e) with FLDL2E; Clang 23 loads it from memory.

A full stack

As a push, FLDL2E needs ST(7) empty. When it was not, Zen 5 pushed the QNaN indefinite with IE masked, setting IE, SF and C1; with IE unmasked it changed no register, and #MF came at the next waiting instruction.

AMD’s Zen 5 guide lists FLDL2E as one macro-op on pipe FP1, one per cycle.

Forms

Every encoding of FLDL2E that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FLDL2E` FLDL2E	`D9 EA`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not empty(st7):
    overflow()
    push(INDEFINITE)
else:
    push(L2E)                        # log2(e)
    c1 = 0
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 8 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FLDL2E`
`ST(0)`	implicit	write
`x87 register stack`	implicit	push
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Its job in exp#

Rounding of the constant#

A full stack#