FLDL2T instruction (x87)

FLDL2T pushes log2(10), about 3.3219, onto the x87 register stack. It is two bytes, D9 E9, and one of the seven constant loads that FLD1’s page describes together. The constant turns a power of 10 into a power of 2, 10^x = 2^(x * log2(10)), the only kind of power the x87 computes, with F2XM1 and FSCALE.

Its job in exp10

With -ffast-math, GCC 14 at -O2 compiles exp10l(x) on a long double to FLD of x, fldl2t and fmulp, then splits the product into an integer and a fraction with FRNDINT and FSUB, raises 2 to the fraction with F2XM1 and an added 1, and scales by the integer with FSCALE. Clang 23 calls the library’s exp10l, with the option or without. As in the exp of FLDL2E’s page, the product is rounded to 64 bits before the split, so the error of the result grows with |x|.

Rounding of the constant

Unlike pi and log2(e), log2(10) lies nearer the 80-bit number below it, and Zen 5 gave that one when rounding to nearest:

RC	Result	Against log2(10)
to nearest, down, toward zero	4000 D49A784B CD1B8AFE	below, by about 0.29 ulp
up	4000 D49A784B CD1B8AFF	above, by about 0.71 ulp

None set PE, and C1 was cleared, as Intel’s manual says for all seven loads; PC at 24 or 53 bits did not shorten the value. Both manuals leave C0, C2 and C3 undefined, and Zen 5 left them as they were in all eight cases. GCC 14 also returns a long double constant equal to log2(10) with FLDL2T; Clang 23 loads the same bits, ending in 8AFE, from memory.

A full stack

As a push, FLDL2T needs ST(7) empty. When it was not, Zen 5 pushed the QNaN indefinite with IE masked, setting IE, SF and C1; with IE unmasked it changed no register, and #MF came at the next waiting instruction.

AMD’s Zen 5 guide lists FLDL2T as one macro-op on pipe FP1, one per cycle.

Forms

Every encoding of FLDL2T that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FLDL2T` FLDL2T	`D9 E9`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not empty(st7):
    overflow()
    push(INDEFINITE)
else:
    push(L2T)                        # log2(10)
    c1 = 0
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 8 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FLDL2T`
`ST(0)`	implicit	write
`x87 register stack`	implicit	push
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Its job in exp10#

Rounding of the constant#

A full stack#