FLDLG2 instruction (x87)

FLDLG2 pushes log10(2), about 0.30103, onto the x87 register stack. It is two bytes, D9 EC, and one of the seven constant loads that FLD1’s page describes together. The x87 has only a binary logarithm, FYL2X, which multiplies log2(x) by the y beneath it; with log10(2) as y the product is the common logarithm, since log10(x) = log10(2) * log2(x).

Its job in log10

With -ffast-math, GCC 14 at -O2 compiles log10l(x) on a long double to three instructions: fldlg2, FLD of x and fyl2x. Clang 23 calls the library’s log10l, with the option or without. The same factor counts decimal digits: an n-bit integer has at most ceil(n * log10(2)) of them, 20 for 64 bits.

Rounding of the constant

log10(2) lies a little nearer the 80-bit number above it, and Zen 5 gave that one when rounding to nearest, as for pi and log2(e):

RC	Result	Against log10(2)
to nearest, up	3FFD 9A209A84 FBCFF799	above, by about 0.44 ulp
down, toward zero	3FFD 9A209A84 FBCFF798	below, by about 0.56 ulp

None set PE, and C1 was cleared; PC at 24 or 53 bits did not shorten the value, and C0, C2 and C3, which both manuals leave undefined, kept their values in all eight cases. GCC 14 returns a long double constant equal to log10(2) with FLDLG2; Clang 23 loads the same bits, ending in F799, from memory.

A full stack

As a push, FLDLG2 needs ST(7) empty. When it was not, Zen 5 pushed the QNaN indefinite with IE masked, setting IE, SF and C1; with IE unmasked it changed no register, and #MF came at the next waiting instruction.

AMD’s Zen 5 guide lists FLDLG2 as one macro-op on pipe FP1, one per cycle.

Forms

Every encoding of FLDLG2 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FLDLG2` FLDLG2	`D9 EC`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not empty(st7):
    overflow()
    push(INDEFINITE)
else:
    push(LG2)                        # log10(2)
    c1 = 0
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 8 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FLDLG2`
`ST(0)`	implicit	write
`x87 register stack`	implicit	push
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Its job in log10#

Rounding of the constant#

A full stack#