FLDLN2 instruction (x87)

FLDLN2 pushes ln(2), about 0.69315, onto the x87 register stack. It is two bytes, D9 ED, and one of the seven constant loads that FLD1’s page describes together. It turns the x87’s binary logarithms into natural ones, ln(x) = ln(2) * log2(x), as the y operand of FYL2X or FYL2XP1.

Its job in log and log1p

With -ffast-math, GCC 14 at -O2 compiles logl(x) on a long double to fldln2, FLD of x and fyl2x. Its log1pl(x) pushes FLDLN2 first and then picks at run time: FYL2XP1 on x itself when |x| is below about 0.2929, the range Intel’s manual gives FYL2XP1, and otherwise FLD1, FADDP and FYL2X on 1 + x. Clang 23 calls the library for both, with the option or without.

Rounding of the constant

ln(2) lies much nearer the 80-bit number above it, and Zen 5 gave that one when rounding to nearest:

RC	Result	Against ln(2)
to nearest, up	3FFE B17217F7 D1CF79AC	above, by about 0.21 ulp
down, toward zero	3FFE B17217F7 D1CF79AB	below, by about 0.79 ulp

None set PE, and C1 was cleared; PC at 24 or 53 bits did not shorten the value, and C0, C2 and C3, which both manuals leave undefined, kept their values in all eight cases.

Not the same as M_LN2

GCC 14 returns a long double constant equal to ln(2) with FLDLN2, and Clang 23 loads the same bits from memory. But M_LN2 in C’s headers is a double constant: returned as a long double, both compilers load the double 3FE62E42FEFA39EF with an 8-byte FLD, a value about 2.3 * 10^-17 below ln(2), not FLDLN2’s. Code that wants the 64-bit constant writes it with an L suffix.

A full stack

As a push, FLDLN2 needs ST(7) empty. When it was not, Zen 5 pushed the QNaN indefinite with IE masked, setting IE, SF and C1; with IE unmasked it changed no register, and #MF came at the next waiting instruction.

AMD’s Zen 5 guide lists FLDLN2 as one macro-op on pipe FP1, one per cycle.

Forms

Every encoding of FLDLN2 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FLDLN2` FLDLN2	`D9 ED`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not empty(st7):
    overflow()
    push(INDEFINITE)
else:
    push(LN2)                        # ln(2)
    c1 = 0
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 8 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FLDLN2`
`ST(0)`	implicit	write
`x87 register stack`	implicit	push
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Its job in log and log1p#

Rounding of the constant#

Not the same as M_LN2#

A full stack#