FLDPI instruction (x87)

FLDPI pushes pi onto the x87 register stack. It is two bytes, D9 EB, and one of the seven constant loads that FLD1’s page describes together: the processor holds pi with more bits than the 80-bit format has and rounds it to 64 bits of significand as RC says.

The two values

Pi lies between two neighbouring 80-bit numbers, and Zen 5 gave one or the other by RC:

RC	Result	Against pi
to nearest, up	4000 C90FDAA2 2168C235	above, by about 0.23 ulp
down, toward zero	4000 C90FDAA2 2168C234	below, by about 0.77 ulp

Neither set PE, and C1 was cleared in all of them. PC changed nothing: at 24 and 53 bits of precision Zen 5 still pushed all 64 bits, since PC applies only to the arithmetic that Intel’s manual lists for it, not to loads. The value to nearest, rounded once more to a double, is the M_PI of C’s headers.

Where compilers use it

GCC 14 at -O2 returns a long double pi written in full with FLDPI. Clang 23 loads the same 80 bits from memory, and GCC does so too for a multiple of pi such as 2 * pi, and for pi itself when built with -m32 -march=i386. In 64-bit code a double pi comes from memory into an XMM register with both.

Not the angle reduction’s pi

FSIN, FCOS and FPTAN reduce their argument by the processor’s internal pi at its full width, which no register can hold. Reducing an angle in software with FLDPI and FPREM1 instead leaves a remainder off by the quotient times FLDPI’s own error, so it grows with the argument.

A full stack

As a push, FLDPI needs ST(7) empty. When it was not, Zen 5 pushed the QNaN indefinite with IE masked, setting IE, SF and C1; with IE unmasked it changed no register, and #MF came at the next waiting instruction.

AMD’s Zen 5 guide lists FLDPI as one macro-op on pipe FP1, one per cycle, like the other constants.

Forms

Every encoding of FLDPI that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FLDPI` FLDPI	`D9 EB`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not empty(st7):
    overflow()
    push(INDEFINITE)
else:
    push(PI)                         # rounded by RC: to nearest, up
    c1 = 0                           # (...C235)
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 8 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FLDPI`
`ST(0)`	implicit	write
`x87 register stack`	implicit	push
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

The two values#

Where compilers use it#

Not the angle reduction’s pi#

A full stack#