FLDZ instruction (x87)

FLDZ pushes +0.0 onto the x87 register stack. It is two bytes, D9 EE, with no memory operand, and one of the seven constant loads that FLD1’s page describes together. Like +1, +0 is exact in every format, so the control word changes nothing: Zen 5 pushed the same 80 zero bits under all four rounding modes and at 24, 53 and 64 bits of precision. The new register is tagged as a zero, and C1 is cleared.

Zero for comparisons

The x87 has no register that reads as zero and no immediate operands, so code that needs a 0 in a register loads it with FLDZ. GCC 14 and Clang 23 at -O2 return a long double 0 that way, and -0.0L as FLDZ followed by FCHS, since no constant is negative. Comparisons with zero load it too: GCC compiles x > 0 to FLDZ, FLD of x, fcomip st, st(1), fstp st(0) and SETA, and both compilers test x == 0 with FLDZ and FUCOMIP.

Before FCOMI, a compare with zero did not need the constant: FTST compares ST(0) with 0 itself. With -m32 -march=i386, GCC compiles x > 0 on a double to FTST, fnstsw ax and a TEST of AH. For x == 0, which C wants quiet for a QNaN, it still loads FLDZ and compares with FUCOMPP: FTST raises the invalid-operation exception for any NaN, as FCOM does.

Stack overflow and the other condition codes

As a push, FLDZ needs ST(7) empty. When it was not, Zen 5 pushed the QNaN indefinite with IE masked, setting IE, SF and C1; with IE unmasked it changed no register, and #MF came at the next waiting instruction. Both manuals leave C0, C2 and C3 undefined; Zen 5 kept them as they were in all eight recorded cases.

AMD’s Zen 5 guide lists FLDZ as one macro-op on pipe FP1, one per cycle, the same as FLD1.

Forms

Every encoding of FLDZ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FLDZ` FLDZ	`D9 EE`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not empty(st7):
    overflow()
    push(INDEFINITE)
else:
    push(to_f80(0))                  # +0
    c1 = 0
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 8 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FLDZ`
`ST(0)`	implicit	write
`x87 register stack`	implicit	push
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Zero for comparisons#

Stack overflow and the other condition codes#