FMUL instruction (x87)

FMUL multiplies ST(0) by another stack register or by a single or double from memory. Its forms follow FADD’s: the product of two registers goes to either of them, and a memory operand, converted exactly, multiplies ST(0). FMULP multiplies into ST(i) and pops, and FIMUL takes an integer from memory. The product is rounded once, to the precision of PC in the direction of RC, and C1 says whether it was rounded up.

In compiled code

Squaring needs no second copy: fmul st, st(0) multiplies ST(0) by itself. GCC 14 at -O2 with -m32, and Clang 23 with -m32 -march=i686 (by default it uses SSE2 there), compile r = x * x; *p = r; return r; on doubles to FLD of x, that FMUL and FST to *p, leaving r in ST(0) as the return value. Where x must survive, they copy it first with fld st(0) and multiply with fmul st, st(1), as the FLD page shows. A multiplication by 2 becomes an addition of ST(0) to itself instead.

Range and special cases

The 80-bit format’s exponent reaches about 10^4932, whatever PC says, so products of doubles that would overflow or underflow in SSE2 stay finite and normal on the stack. Intel’s optimization manual advises keeping intermediate results on the x87 stack for that reason, storing only the final one (Section 3.9.2.2). Zero times infinity is an invalid operation, which with IE masked gives the QNaN indefinite; a denormal operand raises DE.

Speed

Intel’s optimization manual says that the x87 multiply is not pipelined, where the scalar SSE multiply may be, and counts that among the reasons to prefer SSE2 (Section 3.9.4). AMD’s Zen 5 guide lists FMUL as one macro-op with one started each cycle, the same as FADD.

Forms

Every encoding of FMUL that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FMUL m32fp` FMUL_ST0_MEMmem32real	`D8 /1`	FPU
`FMUL ST(0), st(i)` FMUL_ST0_X87	`D8 C8+i`	FPU
`FMUL m64fp` FMUL_ST0_MEMm64real	`DC /1`	FPU
`FMUL st(i), ST(0)` FMUL_X87_ST0	`DC C8+i`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(dest) or empty(src):
    underflow()                  # IE, SF, C1 = 0
    dest.write(INDEFINITE)       # the QNaN indefinite
else:
    dest.write(mul(dest, src))   # C1 = 1 if rounded up
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 65 cases.

Memory forms

if empty(st0):
    underflow()                  # IE, SF, C1 = 0
    st0 = INDEFINITE
else:
    st0 = mul(st0, src)          # a single or double: exact in the
                                 # 80-bit format
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 23 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FMUL m32fp` `FMUL m64fp`
`m32/64fp`	explicit	read
`x87 status word`	implicit	write
`FMUL ST(0), st(i)`
`ST(0)`	explicit	read, write
`st(i)`	explicit	read
`x87 status word`	implicit	write
`FMUL st(i), ST(0)`
`st(i)`	explicit	read, write
`ST(0)`	explicit	read
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

In compiled code#

Range and special cases#

Speed#