FNCLEX instruction (x87)

FNCLEX clears the x87’s exception flags: IE, DE, ZE, OE, UE and PE in the status word, and with them SF, the summary bit ES and the busy bit B. Nothing else changes. The control word, TOP, the tags and the registers stay as they were, which is the difference from FNINIT, the full reset. FCLEX, listed on this page, is FWAIT followed by FNCLEX: 9B DB E2 against DB E2.

Sticky flags

The exception flags are sticky: an instruction sets the flag of each exception it raises and never clears one, so the status word collects every exception since the flags were last cleared, masked or not. Code that wants to know whether one computation raised IE or PE clears the flags first and reads them with FNSTSW afterwards. In C that is feclearexcept and fetestexcept; GCC 14 and Clang 23 at -O2 compile both to calls of the library, which on x86-64 must clear MXCSR’s flags as well, since FNCLEX leaves the SSE side alone.

No wait, and the exception handler

An unmasked exception sets its flag and ES, and the #MF comes at the next x87 instruction that waits. ES stays set until something clears it, so an #MF handler that returns into x87 code has to clear the flags first, or the next waiting instruction faults again. FNCLEX is the one to use there: it does not wait, and so does not fault itself. Zen 5 ran it with IE, with UE and PE, and with ZE and OE flagged, ZE unmasked and ES set: there was no #MF, and every flag, ES included, was clear afterwards. With FCLEX, the FWAIT in front would have raised the #MF first.

Both manuals leave C0 to C3 undefined after FNCLEX; Zen 5 kept them as they were in all five recorded cases. FNCLEX raises no floating-point exception of its own, only #NM when CR0.EM or CR0.TS is set.

AMD’s Zen 5 instruction table has no row for FNCLEX.

Forms

Every encoding of FNCLEX that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FNCLEX` FNCLEX	`DB E2`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

ie = de = ze = oe = ue = pe = 0      # and ES and B, which follow
stack_fault = 0
c0 = c1 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 5 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FNCLEX`
`x87 status word`	implicit	write

Flags

U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	U	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Sticky flags#

No wait, and the exception handler#