FNINIT instruction (x87)

FNINIT puts the x87 unit in its initial state:

the control word becomes 037FH: every exception masked, 64 bits of precision, rounding to nearest (see FLDCW);
the status word becomes 0: no exception flags, C0 to C3 clear, TOP 0;
every register is tagged empty;
the last instruction pointer, data pointer and opcode are cleared, which the 80387 did not do, Intel’s manual notes.

The XMM registers and MXCSR stay as they were. FINIT, listed on this page, is FWAIT followed by FNINIT.

The registers keep their bits

FNINIT only marks the registers empty; it does not zero them, as AMD’s manual says. On Zen 5, an FNSAVE right after it still stored the eight old values, now numbered from TOP 0. An x87 instruction cannot read them any more, since an empty register is a stack underflow, but they are not erased. Initializing the x87 state through XRSTOR, with its bit clear in XSTATE_BV, does zero them, besides setting the same control and status words.

No wait

The N means that FNINIT does not first check for a pending unmasked exception. With ES set in the status word, Zen 5 ran it without #MF, and the exception was gone: FNINIT clears the flags that would have raised it. FINIT’s FWAIT would deliver that #MF first. So FNINIT is the way to reset the unit when its state is unknown or broken, for example in an exception handler that will not resume the faulting code.

In practice

C has no way to ask for FNINIT short of inline assembly, and compiled code does not need it. A function that leaves values on the stack, or MMX code without EMMS, makes later x87 loads overflow, and FNINIT is the blunt repair, which discards the control word too. FNCLEX clears only the exception flags, FFREE empties one register, and FLDENV or FRSTOR load a saved state.

Forms

Every encoding of FNINIT that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FNINIT` FNINIT	`DB E3`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

fcw = 0x037F                         # every exception masked, 64 bits,
                                     # to nearest
fsw = 0                              # TOP 0, no flags, C0-C3 0
ftw = 0xFFFF                         # every register empty; their values
                                     # stay

Run on AMD Zen 5 (EPYC 9645): 5 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FNINIT`
`x87 control word`	implicit	write
`x87 tag word`	implicit	write
`x87 status word`	implicit	write

Flags

M modified; blank: not affected. How to read.

C0	C1	C2	C3
All forms
M	M	M	M

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

The registers keep their bits#

No wait#

In practice#