FNSTCW instruction (x87)

FNSTCW stores the x87 control word, its exception masks, precision control and rounding control, to two bytes of memory. The FLDCW page describes the word’s fields; FNSTCW is how code reads them, usually to save the word before changing it and to put it back afterwards. Unlike FNSTSW, it has no form that writes AX: the destination is always memory.

N for no wait

FNSTCW does not check for a pending unmasked x87 exception first. FSTCW, which this page lists too, is FWAIT followed by FNSTCW, the 9B byte in front, and so takes any pending #MF before storing. On Zen 5, with an unmasked exception flagged in the status word, FNSTCW stored the word and the #MF came only at the FWAIT after it. GCC and Clang emit the no-wait form.

What comes back

Zen 5 stored values such as 037FH, the one FNINIT sets, 0C40H and 1F7FH exactly as they were in effect, bit 12, the infinity control that no longer does anything, included. The condition codes are undefined in Intel’s and AMD’s manuals; Zen 5 left them as they were, and the status word too.

Around a conversion

Before SSE3’s FISTTP, a C cast of a floating-point value to an integer on the x87 had to switch the rounding to toward zero. With -m32 -march=i386, GCC 14 and Clang 23 at -O2 compile (int)x on a long double to FNSTCW into a stack slot, a 16-bit load of it, an OR that sets RC to 11, a 16-bit store of the copy, FLDCW of the copy, FISTP and FLDCW of the saved word. Both keep the accesses to the word at 16 bits, as Intel’s optimization manual advises: reading the stored word back with a load of another size defeats store forwarding (Section 3.9.3.1).

AMD’s Zen 5 guide lists FNSTCW as microcoded, as it does FNSTSW and FLDCW.

Forms

Every encoding of FNSTCW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FNSTCW m16` FNSTCW_MEMmem16	`D9 /7`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dest.write(fcw)
c0 = c1 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FNSTCW m16`
`m16`	explicit	write
`x87 control word`	implicit	read
`x87 status word`	implicit	write

Flags

U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	U	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

N for no wait#

What comes back#

Around a conversion#