FNSTSW instruction (x87)

FNSTSW stores the x87 status word to 16 bits of memory or to AX. The word holds the six exception flags (bits 0 to 5), the stack fault SF (bit 6), the error summary ES (bit 7), the condition codes C0, C1 and C2 (bits 8 to 10) and C3 (bit 14), TOP (bits 13:11) and the busy bit B (bit 15). The N means no wait: FNSTSW does not first check for a pending unmasked exception, so an exception handler can read the word that describes it. FSTSW, listed on this page, is FWAIT followed by FNSTSW. The AX form writes AX alone; the rest of RAX stays.

Branching on the condition codes

Before FCOMI, the compares and FPREM reported only in C0 to C3, and FNSTSW AX was the way to branch on them. In AH, C0 lands in bit 0, C2 in bit 2 and C3 in bit 6, the places of CF, PF and ZF in the flags, so SAHF turns a compare’s result into the pattern FCOMI produces. Compiled code still shows both ways:

GCC 14 at -O2 with -m32 -march=i386 compiles a < b on doubles to an FCOMP, fnstsw ax and test ah, 69, that is C0, C2 and C3 together; none set means b was greater.
GCC inlines fmodl as a loop of FPREM, fnstsw ax, test ah, 4 and a JNE back while C2 says the reduction is not complete.

In 64-bit mode SAHF exists only where CPUID 80000001H ECX[0] reports it; GCC’s TEST of AH needs no such check.

Cost

AMD’s Zen 5 guide lists FNSTSW as microcoded and advises against putting other instructions between a compare and the FNSTSW that reads its result (Section 2.11.3). FNSTCW stores the control word the same way, and FNSTENV the whole environment.

In the optimization guide

What the optimization guide says about FNSTSW, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Silvermont to Goldmont Plus

Vectors and cryptography: Prefer SSE to x87, and fcomi to fcom with fnstsw, on these cores.

Forms

Every encoding of FNSTSW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FNSTSW m16` FNSTSW_MEMmem16	`DD /7`	FPU
`FNSTSW AX` FNSTSW_AX	`DF E0`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dest.write(fsw)                      # with TOP, ES and B; AX: bits 63:16
                                     # of RAX stay
c0 = c1 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 12 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FNSTSW m16`
`m16`	explicit	write
`x87 status word`	implicit	read, write
`FNSTSW AX`
`AX`	explicit	write
`x87 status word`	implicit	read, write

Flags

U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	U	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Branching on the condition codes#

Cost#