Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

FPATAN takes a point (x, y), with x in ST(0) and y in ST(1), and replaces ST(1) by its angle from the positive x axis, then pops, so the angle ends up in ST(0). That is C’s atan2(y, x): the arctangent of y / x placed in the quadrant of the point, from -pi to +pi, with the sign of y. The arctangent of a single number is FPATAN with x = 1.

Any operands

The 80287 accepted only 0 <= |y| < |x| < infinity, Intel’s manual notes; later FPUs accept any pair. Zeros and infinities are not invalid operations as they are for a division: both manuals give 0/0 and infinity/infinity the angles that C’s atan2 gives, and Zen 5 followed their tables for every pair of signed zeros, ones and infinities:

  • y = +0 or -0 gives a zero of y’s sign when x is +0 or positive, and pi of y’s sign when x is -0 or negative;
  • x = +0 or -0 with any other y gives pi/2 of y’s sign;
  • x = +infinity gives a zero of y’s sign for a finite y, and x = -infinity pi of y’s sign;
  • two infinities give pi/4 or 3 * pi / 4, of y’s sign.

Every angle other than 0 comes rounded by RC, with PE. To nearest, pi is rounded up to a value a little above pi, and C1 says so.

Other edges

A NaN in either register gives a NaN; an SNaN or an unsupported encoding is invalid (IE). A denormal operand sets DE, and a tiny ratio can underflow: y = 1 over the largest 80-bit number gave a denormal with UE and PE. For ordinary operands the page’s pseudocode checks Zen 5’s results within 1 ulp (1.5 when not rounding to nearest), and the worst of its 46 recorded results was 0.45 ulp to nearest and 0.77 in the other modes.

From C

GCC 14 and Clang 23 at -O2 compile atanl and atan2l on a long double to calls of the library. With -ffast-math, GCC emits fld1 and fpatan for atanl(x), and fpatan alone for atan2l(y, x) (which needs -fno-math-errno besides -funsafe-math-optimizations); Clang 23 still calls the library.

AMD’s Zen 5 guide lists FPATAN as microcoded.

Forms

Every encoding of FPATAN that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
FPATAN FPATAND9 F3FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = st0
y = st1
if empty(st0) or empty(st1):
    underflow()                  # IE, SF, C1 = 0
    st1 = INDEFINITE
else:
    st1 = atan2(y, x)            # the angle of the point (x, y),
                                 # -pi to pi, within 1 ulp (1.5 when
                                 # not rounding to nearest); Zen 5's
                                 # 46 recorded results: 0.45 at most
                                 # to nearest, 0.77 in the other
                                 # modes. Zeros and
                                 # infinities give 0, or pi, pi/2,
                                 # pi/4, 3pi/4 rounded by RC
pop()
c0 = c2 = c3 = UNDEFINED         # Zen 5 keeps them

Run on AMD Zen 5 (EPYC 9645): 67 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
FPATAN
ST(0)implicitread
ST(1)implicitread, write
x87 register stackimplicitpop
x87 status wordimplicitwrite

Flags

M modified, U undefined; blank: not affected. How to read.
C0C1C2C3
All forms
UMUU

Attributes

What else XED records about the forms. How to read.

All forms
may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
X87

FPU
CPUID.01H:EDX[0] FPU

Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-364 (FPATAN)
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  5. AMD64 Architecture Programmer's Manual, Volume 5: 64-Bit Media and x87 Floating-Point Instructions (26569, rev. 3.16, November 2021), Wayback Machine copy of AMD's PDF
  6. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.