FPREM instruction (x87)

FPREM replaces ST(0) by the remainder of ST(0) divided by ST(1), with the quotient truncated toward zero: C’s fmod. The remainder has the sign of the dividend, 7 and -7 by 2 giving 1 and -1, and it is always exact, so FPREM never raises PE. FPREM keeps the definition of the 8087 and the 287; FPREM1 rounds the quotient to the nearest integer instead, the remainder of IEEE 754 and C’s remainder.

A partial remainder

One FPREM finishes only when the exponents of ST(0) and ST(1) differ by less than 64. Otherwise it takes only the top bits of the quotient, leaves a partial remainder whose exponent is at least 32 lower, and sets C2 to say that the job is not done: for 10^30 by 1, Zen 5 went from an exponent of 99 to one of 62 and set C2. Code therefore runs FPREM in a loop until C2 is clear. GCC 14 at -O2 compiles fmodl(x, y) on a long double, and even fmod on a double, to that loop: fprem, FNSTSW to AX, test ah, 4 (C2 is bit 10 of the status word) and a jne back, calling the library only when the result is a NaN, for the sake of errno. Clang 23 calls the library. remainderl is the same loop around FPREM1.

The quotient’s low bits

Once C2 is clear, C0, C3 and C1 hold bits 2, 1 and 0 of the quotient: 7 by 2 left C3 and C1 set for a quotient of 3. A routine that reduces an angle by pi/4 learns from them which octant it lies in.

The edges

Division by zero and an infinite dividend are invalid operations: IE, and with it masked the QNaN indefinite. An infinite divisor or a zero dividend leaves ST(0) as it was. A denormal operand sets DE, and the remainder may be a denormal, exact and without UE while UE is masked.

AMD’s Zen 5 guide lists FPREM as two macro-ops, of which a core starts one every nine cycles at most; a remainder of numbers far apart takes several of them.

Forms

Every encoding of FPREM that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FPREM` FPREM	`D9 F8`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

c2 = 0                           # first: an exception leaves it 0
if empty(st0) or empty(st1):
    underflow()                  # IE, SF, C1 = 0
    st0 = INDEFINITE             # C0 and C3 stay
else:
    r = prem(st0, st1)           # ST(0) - q * ST(1), exact, with q =
                                 # ST(0) / ST(1) truncated toward zero
    st0 = r
    c1 = r.quotient & 1          # q's low three bits: C0, C3, C1
    if r.partial:                # the exponents were 64 or more apart:
        c2 = 1                   # q had only the quotient's top 32 to
        c0 = c3 = 0              # 63 bits; run FPREM again
    elif not is_nan(r):          # a NaN leaves C0 and C3
        c3 = r.quotient >> 1 & 1
        c0 = r.quotient >> 2 & 1

Run on AMD Zen 5 (EPYC 9645): 56 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FPREM`
`ST(0)`	implicit	read, write
`ST(1)`	implicit	read
`x87 status word`	implicit	write

Flags

M modified; blank: not affected. How to read.

C0	C1	C2	C3
All forms
M	M	M	M

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

A partial remainder#

The quotient’s low bits#

The edges#