FPREM1 instruction (x87)

FPREM1 replaces ST(0) by the remainder of ST(0) divided by ST(1), with the quotient rounded to the nearest integer and ties going to the even one: the remainder of IEEE 754, C’s remainder. Its magnitude is at most half of ST(1)’s, and its sign is whichever makes it so, not the dividend’s; only a zero remainder keeps the dividend’s sign. FPREM truncates the quotient instead, as the 8087 and the 287 did, C’s fmod. Its page covers what they share: the partial remainder with C2 set, the loop that finishes it, and the low quotient bits in C0, C3 and C1.

Rounding the quotient

On Zen 5:

Operands	FPREM1	Quotient
7 by 2	-1	4
5 by 2	1	2, the even one of 2 and 3
7.5 by 1	-0.5	8
6.5 by 1	0.5	6
10 by 0.1, the nearest 80-bit number	about -1.4 * 10^-19	100

Where FPREM’s results are all positive here, FPREM1’s are as close to zero as the quotient allows. In the last row FPREM1 shows how far 10 is from a multiple of the divisor, where FPREM would give almost a whole 0.1. RC plays no part: the remainder is exact, so it never sets PE, and 1.5 by 1 gave -0.5 under rounding toward zero too.

From C

GCC 14 at -O2 compiles remainderl(x, y) on a long double, and remainder on a double, to the loop of fprem1, FNSTSW AX, test ah, 4 and a jne back, calling the library only when the result is a NaN, for errno; with -ffast-math the call goes. Clang 23 calls the library in both cases.

Tiny remainders

The remainder of two normal numbers can be a denormal: 1.5 * 2^-16382 by 2^-16382 gave -2^-16383, exact and without UE while UE was masked. With UE unmasked, Zen 5 left the remainder with its exponent raised by 24576, -2^8193 in place of -2^-16383, set UE and raised #MF.

AMD’s Zen 5 guide lists FPREM1 like FPREM: two macro-ops, of which a core starts one every nine cycles at most.

Forms

Every encoding of FPREM1 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FPREM1` FPREM1	`D9 F5`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

c2 = 0                           # first: an exception leaves it 0
if empty(st0) or empty(st1):
    underflow()                  # IE, SF, C1 = 0
    st0 = INDEFINITE             # C0 and C3 stay
else:
    r = prem1(st0, st1)          # ST(0) - q * ST(1), exact, with q =
                                 # ST(0) / ST(1) to the nearest integer,
                                 # even on a tie: IEEE's remainder
    st0 = r
    c1 = r.quotient & 1          # q's low three bits: C0, C3, C1
    if r.partial:                # the exponents were 64 or more apart:
        c2 = 1                   # q had only the quotient's top 32 to
        c0 = c3 = 0              # 63 bits, truncated; run it again
    elif not is_nan(r):          # a NaN leaves C0 and C3
        c3 = r.quotient >> 1 & 1
        c0 = r.quotient >> 2 & 1

Run on AMD Zen 5 (EPYC 9645): 34 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FPREM1`
`ST(0)`	implicit	read, write
`ST(1)`	implicit	read
`x87 status word`	implicit	write

Flags

M modified; blank: not affected. How to read.

C0	C1	C2	C3
All forms
M	M	M	M

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Rounding the quotient#

From C#

Tiny remainders#