FPTAN instruction (x87)

FPTAN replaces ST(0), an angle in radians, by its tangent, then pushes 1.0: ST(0) holds 1 and ST(1) the tangent. The push is kept for the sake of the 8087 and 80287, Intel’s manual says, and it suggests a use for the 1.0: an FDIVR right after it gives the cotangent, fdivrp st(1), st dividing ST(0) by ST(1). FPTAN shares FSIN’s range: an angle of 2^63 or more in magnitude sets C2, pushes nothing and leaves ST(0) as it was. FSINCOS pushes too, and needs the same free register: with ST(7) full, FPTAN is a stack overflow, and with IE masked ST(0) and ST(1) both become the QNaN indefinite.

No pole

Like FSIN, FPTAN reduces the angle by the x87’s 66-bit pi, and the error grows near every nonzero multiple of pi/2, where the tangent is very small or very large; Intel’s manual advises reducing angles in software to below about 3 * pi / 8. No 80-bit number is exactly pi/2, so the tangent is always finite, with neither ZE nor OE. For pi/2 rounded to 64 bits, whose true tangent is about -3.99 * 10^19, Zen 5 returned exactly -2^65, about -3.69 * 10^19, 7.5 percent away. For reduced angles the page’s pseudocode checks Zen 5’s results within 1 ulp (1.5 in the directed modes), and the worst of its 28 recorded results was 0.56 ulp when rounding to nearest, 0.99 in the directed modes.

Other edges

+0 and -0 are returned exactly, under the 1.0.
A denormal angle is its own tangent, with DE, UE and PE.
Infinities, SNaNs and unsupported encodings are invalid operations (IE). Intel’s pseudocode pushes 1.0 whatever the result, but when the result was a NaN, Zen 5 pushed that NaN instead: a QNaN came back twice, and an infinity gave two indefinites.

From C

GCC 14 at -O2 compiles tanl(x) on a long double to a call of the library. With -funsafe-math-optimizations (part of -ffast-math) it emits fptan followed by fstp st(0), which drops the 1.0; for 1.0L / tanl(x) it drops it all the same and loads a new one with FLD1 before fdivrp st(1), st. With -m32 -march=i386 it does the same for tan on a double. Clang 23 calls tanl even with -ffast-math.

AMD’s Zen 5 guide lists FPTAN as microcoded.

Forms

Every encoding of FPTAN that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FPTAN` FPTAN	`D9 F2`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = st0
big = not less(abs(x), 2 ** 63)  # |x| >= 2^63 (or no number)
if empty(st0):
    underflow()                  # IE, SF, C1 = 0
    st0 = INDEFINITE
    push(INDEFINITE)
    c2 = 0
elif not empty(st7):
    overflow()                   # IE, SF, C1 = 1
    st0 = INDEFINITE
    push(INDEFINITE)
    c2 = 0
elif big and is_finite(x):
    c1 = 0                       # out of range: nothing pushed
    c2 = 1
else:
    t = tan(x)                   # within 1 ulp (1.5 when not
    st0 = t                      # rounding to nearest); Zen 5's 28
                                 # recorded results: 0.56 at most to
                                 # nearest, 0.99 in the other modes
    push(t if is_nan(t) else to_f80(1))   # 1.0, as the 8087
                                 # did: FDIVR then gives the
                                 # cotangent; a NaN twice
    c2 = 0
c0 = c3 = UNDEFINED              # Zen 5 keeps them
# tan(x) is the tangent of x * pi / Pi, where Pi is the 66-bit pi
# by which the processor reduces x, as FSIN

Run on AMD Zen 5 (EPYC 9645): 54 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FPTAN`
`ST(0)`	implicit	read, write
`ST(1)`	implicit	write
`x87 register stack`	implicit	push
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	M	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

No pole#

Other edges#

From C#