FRNDINT instruction (x87)

FRNDINT rounds ST(0) to an integral value in the direction that the control word’s RC selects, and keeps it as a floating-point number in ST(0). PC does not apply. Where FISTP stores an integer of 16, 32 or 64 bits and fails on what does not fit, FRNDINT has nothing to overflow: every number of 2^63 or more in magnitude is an integer already and comes back unchanged.

Where compilers use it

With RC as C programs keep it, to nearest, FRNDINT is rintl: GCC 14 at -O2 compiles rintl(x) on a long double to a bare frndint. For floorl, ceill and truncl it stores the control word with FNSTCW, loads a copy with RC set to down, up or toward zero with FLDCW, runs FRNDINT and loads the saved word back, all inline. nearbyintl stays a call of the library unless -ffast-math is given, because it must not raise the inexact exception that FRNDINT raises. roundl, whose ties go away from zero as no RC does, is a call too; with -ffast-math GCC adds 0.5 to |x|, rounds down and restores the sign. Clang 23 calls the library for all of them. For doubles in SSE registers, SSE4.1’s ROUNDSD takes the direction from its immediate and can suppress the inexact exception.

The edges

Ties to nearest go to the even integer: 2.5 gave 2, -2.5 gave -2 and 1.5 gave 2, the last with C1 set because it was rounded up.
A changed value raises PE; an integer, a zero or an infinity comes back unchanged without it.
The sign survives a result of zero: -0.1 to nearest and -0.5 rounded up gave -0.
A denormal sets DE and PE: rounded up, the smallest gave 1.
An SNaN or an unsupported encoding is invalid: IE, and with it masked the QNaN indefinite.

Cost

AMD’s Zen 5 guide lists FRNDINT as one macro-op, of which a core starts one per cycle, unlike the microcoded transcendental instructions; the FLDCW pair around it for floorl is microcoded.

Forms

Every encoding of FRNDINT that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FRNDINT` FRNDINT	`D9 FC`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(st0):
    underflow()                  # IE, SF, C1 = 0
    st0 = INDEFINITE
else:
    st0 = round(st0)             # to an integral value by RC; PE when
                                 # it changes, C1 = 1 if rounded up
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 27 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FRNDINT`
`ST(0)`	implicit	read, write
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Where compilers use it#

The edges#

Cost#