FRSTOR instruction (x87)

FRSTOR loads the whole x87 state from memory: the environment that FLDENV loads, then the eight data registers, ten bytes each in stack order, ST(0) first. It reads what FNSAVE stores, 108 bytes with a 32- or 64-bit operand size and 94 with the 66 prefix, whose environment has 16-bit pointers and no opcode. Unlike FNSAVE, it has no no-wait twin: a pending unmasked exception raises #MF first, and on Zen 5 nothing was loaded.

What it loads, and what it works out

The registers go where the loaded TOP puts them, so the image’s ST(0) is ST(0) again whatever TOP was before. Three parts of the environment are not taken as stored:

The tag word says only which registers are empty; for the others the processor classifies the contents itself, as Intel’s manual says. Zen 5 turned a stored tag word of 0, all valid, into zero and special tags where the registers held them.
ES and B follow the loaded flags and masks: an image with both set but every exception masked came back with them clear.
The control word keeps its defined bits; from FFFFH, Zen 5 kept 1F7FH, with bit 6 set and bits 7 and 13 to 15 clear.

An image whose status word holds an unmasked exception flag makes it pending again: Zen 5 loaded a ZE flag with ZE unmasked, and #MF came at the next waiting instruction. Intel’s manual suggests clearing the flags in the image when that is not wanted. This site’s probe loads every x87 case’s starting state with FRSTOR and reads the result back with FNSAVE.

Its place today

FNSAVE and FRSTOR were how an operating system switched x87 state before FXSAVE and FXRSTOR, which Intel’s manual recommends for context switches; it still calls FNSAVE and FRSTOR the cheaper pair for moving between x87 and MMX code within a program. Neither saves XMM registers, and in 64-bit mode the environment holds only 32 bits of each pointer. Compilers have no intrinsic for FRSTOR, and AMD’s Zen 5 guide lists it, like FNSAVE, as microcoded.

Forms

Every encoding of FRSTOR that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FRSTOR m94byte` FRSTOR_MEMmem94	`66 DD /4`	FPU
`FRSTOR m108byte` FRSTOR_MEMmem108	`REX.W DD /4` `DD /4`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

FRSTOR m108byte

a = src.address
t = load(a + 4, 16) >> 11 & 7    # the TOP it loads
for i in range(8):
    v = load(a + 28 + 10 * i, 80)
    st[(t - top + i) % 8] = v    # ST(i) once TOP is t
fcw = load(a, 16) & 0x1F3F | 0x40   # the environment, as FLDENV
fsw = load(a + 4, 16)            # loads it: ES and B follow
ftw = load(a + 8, 16)            # only which are empty
fip = load(a + 12, 32)
fcs = load(a + 16, 16)
fop = load(a + 18, 16) & 0x7FF
fdp = load(a + 20, 32)
fds = load(a + 24, 16)

Run on AMD Zen 5 (EPYC 9645): 6 cases.

FRSTOR m94byte

a = src.address
t = load(a + 2, 16) >> 11 & 7    # the TOP it loads
for i in range(8):
    v = load(a + 14 + 10 * i, 80)
    st[(t - top + i) % 8] = v    # ST(i) once TOP is t
fcw = load(a, 16) & 0x1F3F | 0x40   # the environment, as FLDENV
fsw = load(a + 2, 16)            # loads it
ftw = load(a + 4, 16)
fip = load(a + 6, 16)
fcs = load(a + 8, 16)
fop = 0
fdp = load(a + 10, 16)
fds = load(a + 12, 16)

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FRSTOR m94byte` `FRSTOR m108byte`
`m94/108byte`	explicit	read
`x87 control word`	implicit	write

Flags

M modified; blank: not affected. How to read.

C0	C1	C2	C3
All forms
M	M	M	M

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

What it loads, and what it works out#

Its place today#