FSCALE instruction (x87)

FSCALE multiplies ST(0) by 2^n, where n is ST(1) truncated toward zero whatever RC says: Zen 5 scaled by 2^-2 for ST(1) = -2.5, and by 2^0 for 0.9 with RC set to round down. ST(1) stays where it is; there is no form that pops, so compiled code follows FSCALE with fstp st(1). It is the x87’s ldexp: with -ffast-math, GCC 14 at -O2 compiles ldexpl(x, n) to FILD of n, fxch, fscale and fstp st(1), and it ends the exp2l and expl sequences that F2XM1’s page shows. Without that option, and with Clang 23 in either case, ldexpl is a call of the library. FXTRACT is its inverse: it splits a number into the exponent and the significand that FSCALE puts back together.

Exact, until the range runs out

Only the exponent changes, so a result in the normal range is exact, without PE. At the ends the result is rounded like any other:

Past the largest exponent, OE and PE: 1 scaled by 2^16384 gave the largest finite number with RC toward zero, and 1 scaled by 2^(10^10) gave +infinity to nearest. A huge n needs no special care.
Into the denormals, rounding only when bits fall off: 1 scaled by 2^-16383 gave an exact denormal with no flag, -1/3 scaled by 2^-16420 one with UE and PE, and 1 scaled by 2^-16446 gave +0 with UE and PE.
With OE or UE unmasked, the x87 delivers the result with its exponent wrapped by 24,576 and raises #MF: Zen 5 left 2^-8192 in ST(0) for 1 scaled by 2^16384, and 2^8130 for 1 scaled by 2^-16446.

Infinite scale factors

An infinite ST(1) gives an infinity (+infinity) or a zero (-infinity) of ST(0)’s sign, exactly. The two products that make no sense are invalid operations, IE and the QNaN indefinite: 0 scaled by 2^+infinity and infinity scaled by 2^-infinity. A denormal ST(0) sets DE and is scaled like any other number.

AMD’s Zen 5 guide lists FSCALE as microcoded, unlike the multiplications, which are not.

Forms

Every encoding of FSCALE that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FSCALE` FSCALE	`D9 FD`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(st0) or empty(st1):
    underflow()                  # IE, SF, C1 = 0
    st0 = INDEFINITE
else:
    st0 = scale(st0, st1)        # ST(0) * 2^n, n = ST(1) truncated
                                 # toward zero; C1 = 1 if rounded up
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 36 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FSCALE`
`ST(0)`	implicit	read, write
`ST(1)`	implicit	read
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Exact, until the range runs out#

Infinite scale factors#