FSIN instruction (x87)

FSIN replaces ST(0), an angle in radians, by its sine. FCOS takes the cosine, FSINCOS both (the sine in ST(1), the cosine on top), and FPTAN the tangent; they share FSIN’s range and its reduction of the angle.

Range

The angle must be smaller than 2^63 in magnitude. Otherwise FSIN sets C2 and leaves ST(0) as it was, with no exception: Zen 5 did so for 2^63 and computed a result for the next smaller number. Code that may see larger angles tests C2 after FSIN (FNSTSW) and reduces the angle itself, by a multiple of 2 * pi, before trying again. Infinities are invalid operations: IE, and with the exception masked the QNaN indefinite.

Accuracy, and the x87’s pi

Within its range FSIN reduces the angle by multiples of an internal pi of 66 bits, which Intel’s manual calls Pi, and only then approximates the sine. So what it computes is the sine of x * pi / Pi, whose period is 2 * Pi, not 2 * pi. Intel’s manual promises an error below 1 ulp (1.5 when not rounding to nearest) only for angles already reduced, and suggests reducing them in software to below about 3 * pi / 4. Near a nonzero multiple of pi, where the sine is small, the 66 bits run out: for pi rounded to 64 bits, Zen 5 returned exactly -2^-64, where the true sine is about -5.017 * 10^-20, 8 percent away. For reduced arguments the page’s pseudocode checks Zen 5’s results within 1 ulp (1.5 when not rounding to nearest), and the worst of its 27 recorded results was 0.47 ulp to nearest and 0.74 in the other modes.

From C

GCC 14 and Clang 23 at -O2 compile sinl(x) on a long double to a call of the library. GCC emits fsin for it only with -funsafe-math-optimizations (part of -ffast-math); Clang 23 calls sinl even then. Neither uses it for sin on a double, which lives in an SSE register.

Speed

AMD’s Zen 5 guide lists FSIN, like the other transcendental instructions, as microcoded. Intel’s optimization manual suggests that software implementations, in SSE or SSE2 where 80 bits are not needed, can be faster than the x87’s transcendentals (Sections 3.9.1 and 3.9.4).

Forms

Every encoding of FSIN that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FSIN` FSIN	`D9 FE`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = st0
big = not less(abs(x), 2 ** 63)  # |x| >= 2^63 (or no number)
if empty(st0):
    underflow()                  # IE, SF, C1 = 0
    st0 = INDEFINITE
    c2 = 0
elif big and is_finite(x):
    c1 = 0                       # out of range: ST(0) stays
    c2 = 1
else:
    st0 = sin(x)                 # within 1 ulp (1.5 when not
    c2 = 0                       # rounding to nearest); Zen 5's 27
                                 # recorded results: 0.47 at most to
                                 # nearest, 0.74 in the other modes
c0 = c3 = UNDEFINED              # Zen 5 keeps them
# sin(x) is the sine of x * pi / Pi, where Pi is the 66-bit pi by
# which the processor reduces x: near a multiple of pi the result is
# far from the sine of x (FSIN of pi rounded to 64 bits is -2^-64)

Run on AMD Zen 5 (EPYC 9645): 48 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FSIN`
`ST(0)`	implicit	read, write
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	M	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Range#

Accuracy, and the x87’s pi#

From C#

Speed#