FSINCOS instruction (x87)

FSINCOS takes an angle in radians from ST(0) and leaves two results: the sine replaces the angle, and the cosine is pushed on top of it. So ST(0) ends up holding the cosine and ST(1) the sine. Intel’s manual calls it faster than FSIN followed by FCOS, whose pages explain the range, below 2^63 in magnitude, and the 66-bit pi by which the x87 reduces an angle; here the error grows near every nonzero multiple of pi/2, and Intel’s manual advises reducing angles in software to below about 3 * pi / 8.

The stack needs room

FSINCOS pushes, so ST(7) must be empty. Otherwise it is a stack overflow: IE, SF and C1 are set, and with IE masked ST(0) and ST(1) both become the QNaN indefinite, so the angle is lost. Zen 5 checked this before the range: 2^63 on a full stack also gave two indefinites. An angle out of range pushes nothing: C2 is set and ST(0) keeps the angle, so code that tests C2 with FNSTSW must not pop two values after it.

Edge cases, and C1

+0 and -0 give a sine of the same zero and a cosine of +1, exact.
An infinity is an invalid operation (IE), with two indefinites when masked; a QNaN comes back twice, and an SNaN twice quieted, with IE.
A denormal angle is its own sine, with DE, UE and PE, and a cosine of 1. With UE unmasked, Zen 5 delivered the sine with its exponent raised by 24,576, the x87’s bias for an unmasked underflow, and #MF came at the next waiting instruction.
AMD’s manual has C1 report the rounding of ST(1), the sine; Intel’s says only that it is set when the result was rounded up. The page’s pseudocode takes C1 from the sine, and Zen 5’s cases agree. For reduced angles its 56 recorded results are within 1 ulp: 0.48 at most to nearest, 0.81 in the directed modes.

From C

GCC 14 at -O2 turns sinl(x) and cosl(x) of one long double into a call of sincosl. With -funsafe-math-optimizations (part of -ffast-math) it emits fsincos instead, then fxch st(1) to bring the sine to the top and two FSTPs. Clang 23 calls sinl and cosl, or sincosl with -ffast-math, and never emits FSINCOS.

AMD’s Zen 5 guide lists FSINCOS as microcoded.

Forms

Every encoding of FSINCOS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FSINCOS` FSINCOS	`D9 FB`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = st0
big = not less(abs(x), 2 ** 63)  # |x| >= 2^63 (or no number)
if empty(st0):
    underflow()                  # IE, SF, C1 = 0
    st0 = INDEFINITE
    push(INDEFINITE)
    c2 = 0
elif not empty(st7):
    overflow()                   # IE, SF, C1 = 1
    st0 = INDEFINITE
    push(INDEFINITE)
    c2 = 0
elif big and is_finite(x):
    c1 = 0                       # out of range: nothing pushed
    c2 = 1
else:
    c = cos(x)                   # within 1 ulp (1.5 when not
    s = sin(x)                   # rounding to nearest); Zen 5's 56
    st0 = s                      # recorded results: 0.48 at most to
                                 # nearest, 0.81 in the other modes.
                                 # C1 is the sine's
    push(c)                      # the cosine on top; a NaN twice
    c2 = 0
c0 = c3 = UNDEFINED              # Zen 5 keeps them
# of x * pi / Pi, where Pi is the 66-bit pi by which the processor
# reduces x, as FSIN and FCOS

Run on AMD Zen 5 (EPYC 9645): 54 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FSINCOS`
`ST(0)`	implicit	read, write
`ST(1)`	implicit	write
`x87 register stack`	implicit	push
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	M	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

The stack needs room#

Edge cases, and C1#

From C#