FSQRT instruction (x87)

FSQRT replaces ST(0) by its square root, rounded once to the precision that the control word’s PC selects, as RC says. Unlike the x87’s transcendental instructions, such as FSIN, it is exact in the IEEE 754 sense: the result is the true root correctly rounded, and C1 says whether it was rounded up. It is the only square root for the 64-bit significand of long double; SQRTSD and SQRTSS do the same for doubles and singles.

The edges

The root of -0 is -0, and that of +infinity is +infinity.
Any other negative number, -infinity included, is an invalid operation: IE, and with it masked the QNaN indefinite. So is an unnormal, an 80-bit encoding with a zero integer bit and a nonzero exponent: Zen 5 answered the unnormal 3FFF4000000000000000H with the indefinite.
A denormal operand sets DE, but its root is a normal number: the smallest denormal, 2^-16445, gave about 1.414 * 2^-8223 with DE and PE.
At PC 24, Zen 5 rounded the root of 0.1 down to 24 bits, setting PE, and the root of the largest 80-bit number up to 2^8192, setting C1 and PE.

From C

C’s sqrtl(x) may set errno for a negative x, as glibc’s does, which FSQRT cannot. At -O2 GCC 14 therefore puts a compare with zero in front of FSQRT and calls the library for negative numbers, while Clang 23 calls sqrtl every time. With -fno-math-errno, both compile sqrtl(x) and __builtin_sqrtl(x) to a bare fld and fsqrt.

Speed

Intel’s optimization manual notes that x87 division and square roots finish sooner at a lower PC (Section 3.9.3.2), so code that needs only double precision can set PC to 53 bits with FLDCW. AMD’s Zen 5 guide lists FSQRT as one macro-op, of which a core starts one every nine cycles at most.

Forms

Every encoding of FSQRT that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FSQRT` FSQRT	`D9 FA`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(st0):
    underflow()                  # IE, SF, C1 = 0
    st0 = INDEFINITE
else:
    st0 = sqrt(st0)              # -0 stays -0; another negative
                                 # number: IE and INDEFINITE
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 25 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FSQRT`
`ST(0)`	implicit	read, write
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

The edges#

From C#

Speed#