FST instruction (x87)

FST copies ST(0) to a single or a double in memory, or to another x87 register, and leaves the stack as it was. FSTP is the same store followed by a pop, and only FSTP can write the 80-bit format: FST has no m80fp form. Compilers use FST where the value is still needed after the store: GCC 14 and Clang 23 at -O2 compile *p = x; return x;, with x a long double and p a double *, to an FLD and fst QWORD PTR [rdi], which leaves x in ST(0) as the result. Without the return x, both use fstp instead.

A store that rounds

A store to m32fp or m64fp rounds the 80-bit value to the destination’s format, as RC says; PC plays no part. So the store can raise the exceptions of any rounding: PE when bits are lost, OE when the value is too large for the format (with OE masked, an infinity or the largest finite number, as RC directs), UE when it is too small. A signaling NaN is stored quiet, with IE. An unmasked overflow or underflow into memory writes nothing.

This rounding is how x87 code gets single or double results at all. Where C asks for a double, the registers hold more: GCC 14 compiles 32-bit code with __FLT_EVAL_METHOD__ 2, evaluating in the 80-bit format, and a value only becomes a double when it is stored. Intel’s optimization manual notes that compilers therefore store and reload values to reduce their precision (Section 3.9.4.1); SSE2’s scalar instructions avoid that.

The register form

FST ST(i) copies ST(0) into ST(i) exactly, whatever it holds, and an empty ST(i) is no fault: it simply becomes full. An empty ST(0) is a stack underflow, which with IE masked stores the QNaN indefinite.

AMD’s Zen 5 guide lists FST to memory as two macro-ops and FST ST(i) as one.

Forms

Every encoding of FST that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FST m32fp` FST_MEMmem32real_ST0	`D9 /2`	FPU
`FST m64fp` FST_MEMm64real_ST0	`DD /2`	FPU
`FST st(i)` FST_X87_ST0	`DD D0+i`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

Memory forms

if empty(st0):
    underflow()
    v = INDEFINITE
else:
    v = st0
if dest.bits == 32:
    dest.write(to_f32(v))        # rounded by RC, not PC; an SNaN
else:                            # stored quiet, with IE
    dest.write(to_f64(v))
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 86 cases.

if empty(st0):
    underflow()
    dest.write(INDEFINITE)
else:
    dest.write(st0)              # as it is; an empty ST(i) is no
    c1 = 0                       # fault
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 8 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FST m32fp` `FST m64fp`
`m32/64fp`	explicit	write
`x87 status word`	implicit	write
`FST st(i)`
`st(i)`	explicit	write
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

A store that rounds#

The register form#