FSTP instruction (x87)

FSTP stores ST(0) and pops it: the store is that of FST, whose page explains the rounding of the single and double forms, and the pop then tags the old ST(0) empty and moves TOP up by one, so that ST(1) becomes ST(0). It is the usual end of an x87 computation: GCC 14 and Clang 23 at -O2 compile *p = x, with x a long double and p a double *, to an FLD of x and fstp QWORD PTR [rdi], which leaves the stack as empty as it was.

The 80-bit store

Only FSTP writes the 10-byte extended format, and it copies the register bit for bit, of any class, with no rounding and no exception: a signaling NaN stays signaling. Code that spills a long double, or saves an x87 register to come back to it, uses FSTP m80fp and FLD m80fp, the one pair that preserves every value.

Popping without storing

FSTP ST(i) copies ST(0) to ST(i) before the pop, so it doubles as a way to discard values:

fstp st(0) drops the top of the stack. Compilers emit it after FCOMIP, which pops only one of the two operands it compared, and to throw away a result nobody uses.
fstp st(1) drops the value below the top and keeps the top: GCC uses it after the FPREM loop it inlines for fmodl, where ST(0) holds the remainder and ST(1) the divisor.

An empty ST(0) is a stack underflow; with IE masked, FSTP stores the QNaN indefinite and still pops.

More encodings

Besides DD D8+i, XED decodes three encodings that it marks as undocumented as FSTP to a register: D9 D8+i (named FSTPNCE), DF D0+i and DF D8+i. Zen 5 ran all three as FSTP ST(i), as the recorded cases show.

AMD’s Zen 5 guide lists FSTP to memory as two macro-ops and FSTP ST(i) as one.

In the optimization guide

What the optimization guide says about FSTP, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Silvermont to Goldmont Plus

Front end: On Silvermont these instructions come from the microcode ROM; Goldmont decodes them directly, except an indirect call through memory.

Forms

Every encoding of FSTP that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FSTP m32fp` FSTP_MEMmem32real_ST0	`D9 /3`	FPU
`FSTP m80fp` FSTP_MEMmem80real_ST0	`DB /7`	FPU
`FSTP m64fp` FSTP_MEMm64real_ST0	`DD /3`	FPU
`FSTP st(i)` FSTP_X87_ST0	`DD D8+i`	FPU
`FSTP st(i)` undocumented FSTP_X87_ST0_DFD0	`DF D0+i`	FPU
`FSTP st(i)` undocumented FSTP_X87_ST0_DFD1	`DF D8+i`	FPU
`FSTP st(i)` undocumented FSTPNCE_X87_ST0	`D9 D8+i`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

FSTP m32fp FSTP m64fp

if empty(st0):
    underflow()
    v = INDEFINITE
else:
    v = st0
if dest.bits == 32:
    dest.write(to_f32(v))        # rounded by RC, not PC
else:
    dest.write(to_f64(v))
pop()
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 40 cases.

FSTP st(i) FSTP m80fp

if empty(st0):
    underflow()
    dest.write(INDEFINITE)
else:
    dest.write(st0)              # as it is, of any class
    c1 = 0
pop()                            # FSTP ST(0): the pop is all
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 29 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FSTP m32fp` `FSTP m64fp` `FSTP m80fp`
`m32/64/80fp`	explicit	write
`x87 register stack`	implicit	pop
`x87 status word`	implicit	write
`FSTP st(i)`
`st(i)`	explicit	write
`x87 register stack`	implicit	pop
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

The 80-bit store#

Popping without storing#

More encodings#