FSUB instruction (x87)

FSUB subtracts the source from the destination and leaves the difference in the destination: fsub st, st(i) computes ST(0) - ST(i) into ST(0), fsub st(i), st computes ST(i) - ST(0) into ST(i), and the memory forms subtract a single or double from ST(0). Its relatives cover the other cases: FSUBP subtracts into ST(i) and pops, FISUB subtracts an integer from memory, and FSUBR swaps the operands; its page has the table of the four register encodings and the order each one means.

In compiled code

For a - b on two long doubles, GCC 14 at -O2 loads a, then b, and emits fsubp st(1), st (DE E9); Clang 23 loads b first and emits fsubrp st(1), st. A double or float in memory stays there: both compile a - *p to FLD of a and fsub QWORD PTR [rdi] (or DWORD PTR). The memory operand becomes an 80-bit value exactly, so the difference is rounded only once, to the precision PC selects. The compilers part ways on the rest:

a - *p with an int is FILD of it and FSUBRP for GCC, while Clang copies the integer to the stack and uses FISUB;
a - 1.0L is FLD1 and FSUBP for GCC, and FLD1, FCHS and FADDP for Clang;
with -ffast-math, GCC’s expl uses fsub st(1), st (DC E9) to split x * log2(e) into an integer and a fraction for F2XM1.

Signed zeros and rounding

A number less itself is +0, except when RC rounds down, where it is -0: Zen 5 gave +0 for a register less itself under rounding to nearest and toward zero, and -0 for 1.5 - 1.5 under rounding down. +infinity less +infinity is an invalid operation: IE, and with IE masked the QNaN indefinite. -infinity less +infinity is -infinity, exactly.

C1 says which way an inexact result went. With PC at 24 bits, 1 less the smallest single denormal gave 1 with DE, PE and C1 = 1: rounded up. Under rounding toward zero, 1 - 10^-30 gave the largest 80-bit number below 1, with PE and C1 = 0.

AMD’s Zen 5 guide lists FSUB, every form alike, as one macro-op on pipe FP2, one per cycle.

Forms

Every encoding of FSUB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FSUB m32fp` FSUB_ST0_MEMmem32real	`D8 /4`	FPU
`FSUB ST(0), st(i)` FSUB_ST0_X87	`D8 E0+i`	FPU
`FSUB m64fp` FSUB_ST0_MEMm64real	`DC /4`	FPU
`FSUB st(i), ST(0)` FSUB_X87_ST0	`DC E8+i`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(dest) or empty(src):
    underflow()                  # IE, SF, C1 = 0
    dest.write(INDEFINITE)       # the QNaN indefinite
else:
    dest.write(sub(dest, src))   # C1 = 1 if rounded up
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 27 cases.

Memory forms

if empty(st0):
    underflow()                  # IE, SF, C1 = 0
    st0 = INDEFINITE
else:
    st0 = sub(st0, src)          # a single or double: exact in the
                                 # 80-bit format
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 12 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FSUB m32fp` `FSUB m64fp`
`m32/64fp`	explicit	read
`x87 status word`	implicit	write
`FSUB ST(0), st(i)`
`ST(0)`	explicit	read, write
`st(i)`	explicit	read
`x87 status word`	implicit	write
`FSUB st(i), ST(0)`
`st(i)`	explicit	read, write
`ST(0)`	explicit	read
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

In compiled code#

Signed zeros and rounding#