FSUBR instruction (x87)

FSUBR subtracts with the operands the other way round from FSUB: the destination receives the source less the destination. fsubr st, st(i) computes ST(i) - ST(0) into ST(0), fsubr st(i), st computes ST(0) - ST(i) into ST(i), and the memory forms compute the single or double less ST(0). FSUBRP does the same into ST(i) and pops, and FISUBR takes an integer. The rounding and exceptions are FSUB’s.

Why the memory forms need it

A memory operand can only be the source, and FSUB subtracts the source from ST(0). To subtract ST(0) from a value in memory, FSUBR does it without loading the value first: GCC 14 and Clang 23 at -O2 compile *y - x, with a long double x and a double y, to FLD of x and fsubr qword ptr [rdi]. With both operands on the stack, they use FSUBRP or FSUBP, whichever matches the order of the loads: 0.0L - x is FLD of x, FLDZ and fsubrp st(1), st (see FCHS for why it is not a negation).

Two bits of the encoding

In the register forms, one opcode bit picks the destination (D8 for ST(0), DC for ST(i)) and the ModRM reg field picks the order of the operands, and the order means the same in both rows: /4 is ST(0) less ST(i), /5 ST(i) less ST(0). Intel’s names say whether the destination is the minuend, so they swap between the rows:

Bytes	Intel name	Result
D8 E0+i	FSUB ST(0), ST(i)	ST(0) - ST(i) into ST(0)
D8 E8+i	FSUBR ST(0), ST(i)	ST(i) - ST(0) into ST(0)
DC E0+i	FSUBR ST(i), ST(0)	ST(0) - ST(i) into ST(i)
DC E8+i	FSUB ST(i), ST(0)	ST(i) - ST(0) into ST(i)

The AT&T syntax names the DC forms the other way round, which is the trap that FDIV’s page describes.

On Zen 5

A register less itself gave +0 under rounding to nearest and toward zero, including through DC E0, fsubr st(0), st. Subtracting -max from +max with OE unmasked left the overflowed result in ST(0) with its exponent reduced by 24576, as Intel’s manual describes for an unmasked overflow, and #MF followed. AMD’s Zen 5 guide lists FSUBR like FSUB: one macro-op on pipe FP2, one per cycle.

Forms

Every encoding of FSUBR that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FSUBR m32fp` FSUBR_ST0_MEMmem32real	`D8 /5`	FPU
`FSUBR ST(0), st(i)` FSUBR_ST0_X87	`D8 E8+i`	FPU
`FSUBR m64fp` FSUBR_ST0_MEMm64real	`DC /5`	FPU
`FSUBR st(i), ST(0)` FSUBR_X87_ST0	`DC E0+i`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(dest) or empty(src):
    underflow()                  # IE, SF, C1 = 0
    dest.write(INDEFINITE)       # the QNaN indefinite
else:
    dest.write(sub(src, dest))   # reversed: the source less the
                                 # destination
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 27 cases.

Memory forms

if empty(st0):
    underflow()                  # IE, SF, C1 = 0
    st0 = INDEFINITE
else:
    st0 = sub(src, st0)          # the single or double less ST(0)
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 12 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FSUBR m32fp` `FSUBR m64fp`
`m32/64fp`	explicit	read
`x87 status word`	implicit	write
`FSUBR ST(0), st(i)`
`ST(0)`	explicit	read, write
`st(i)`	explicit	read
`x87 status word`	implicit	write
`FSUBR st(i), ST(0)`
`st(i)`	explicit	read, write
`ST(0)`	explicit	read
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Why the memory forms need it#

Two bits of the encoding#

On Zen 5#