FTST instruction (x87)

FTST compares ST(0) with zero and reports the answer in the condition codes, as FCOM does with another value: C3, C2 and C0 clear when ST(0) is greater, C0 set when it is less, C3 set when it is zero of either sign, and all three when it is a NaN or unsupported. C1 is cleared. It is two bytes, D9 E4, with no operand, needs no zero in a register and pops nothing.

A signaling compare

Intel’s manual calls the comparison unordered, but that only names the fourth outcome: FTST raises the invalid-operation exception for a NaN of either kind, as FCOM does, not only for a signaling one as FUCOM does. AMD’s manual lists QNaNs among its IE causes too, and Zen 5 raised IE for QNaNs of both signs, an SNaN and the unsupported encodings it was given (an unnormal, a pseudo-infinity and a pseudo-NaN). A denormal raises DE and compares as its value, which is never zero: Zen 5 reported a positive denormal as greater.

With IE unmasked, Intel’s table does not say whether the codes are written. Zen 5 wrote them as unordered for a QNaN and for an empty ST(0), cleared C1, and #MF came at the next waiting instruction; with DE unmasked it wrote the result of the compare. With an exception already pending, the #MF came at FTST itself and the codes stayed.

Where it still appears

C’s x > 0 may raise the invalid exception for a NaN, so it can use FTST, and GCC 14 does at -O2 with -m32 -march=i386 on a double: FLD, FTST, FNSTSW AX, fstp st(0) and test ah, 69, which is true only when all three codes are clear. For x == 0, which must stay quiet, it loads FLDZ and uses FUCOMPP instead. On processors with FCOMI, and in 64-bit code, compilers compare with an FLDZ and FCOMIP or FUCOMIP, which set RFLAGS directly; FTST has no form that does. Clang 23 used no FTST in these tests, even for i386: it loads FLDZ and compares with FUCOMPP.

FXAM classifies ST(0) without raising anything. AMD’s Zen 5 guide lists FTST as one macro-op on pipe FP1, one per cycle.

Forms

Every encoding of FTST that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FTST` FTST	`D9 E4`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(st0):
    underflow()
    x = 3                            # unordered
else:
    x = comi(st0, 0)                 # against +0; any NaN raises IE
c3 = x in (2, 3)                     # set with IE or DE unmasked too
c2 = x == 3
c0 = x in (1, 3)
c1 = 0

Run on AMD Zen 5 (EPYC 9645): 22 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FTST`
`ST(0)`	implicit	read, write
`x87 status word`	implicit	write

Flags

M modified; blank: not affected. How to read.

C0	C1	C2	C3
All forms
M	M	M	M

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

A signaling compare#

Where it still appears#