FUCOM instruction (x87)

FUCOM compares ST(0) with ST(i), or with ST(1) when no register is named, and sets C0, C2 and C3 of the x87 status word the way FCOM does: all clear for greater, C0 for less, C3 for equal (-0 equals +0), all three for unordered; C1 is cleared. FCOM’s page has the table and how the codes reach RFLAGS. The U stands for unordered: a quiet NaN gives unordered without the invalid-operation exception (IE), which FCOM raises for any NaN. FUCOM has no memory form. FUCOMP pops once after the compare, and FUCOMPP, which compares ST(0) with ST(1), pops twice. Intel’s manual dates the three to the Intel 387; from the P6 family on, FUCOMI writes RFLAGS directly.

Without FUCOMI

GCC 14 and Clang 23 at -O2 with -m32 -march=i386 compile a compare of two doubles to two FLDs, a compare and FNSTSW AX:

a == b: GCC uses FUCOMPP, then and ah, 69 and cmp ah, 64, since C3 alone means equal and C3 with C2 and C0 means unordered. Clang uses FUCOMPP and SAHF, which puts C0, C2 and C3 in CF, PF and ZF, then SETE and SETNP.
a < b: GCC uses the signaling FCOMP, as C’s relational operators ask, and keeps FUCOMPP for isless(a, b). Clang uses FUCOMPP and SETA for both, so its a < b raises no IE for a QNaN.
__builtin_isnan(x): both use fucomp st(0), since only a NaN is unordered with itself, and test C2.

What Zen 5 did

A QNaN gave unordered and no IE, even with IE unmasked.
An SNaN, or an unsupported encoding (an unnormal, a pseudo-infinity, a pseudo-NaN), raised IE and gave unordered.
An empty register raised IE and SF, with C1 = 0, and gave unordered.
A denormal raised DE and was compared: the smallest denormal came out greater than +0.

Intel’s manual says that an unmasked IE leaves the condition codes alone. With IE unmasked, Zen 5 still set them to unordered, for an SNaN and an empty register alike, and with DE unmasked to the compare’s result; #MF came at the next waiting instruction, and FUCOMP and FUCOMPP did not pop after an unmasked IE.

AMD’s Zen 5 guide lists FUCOM, FUCOMP and FUCOMPP as one macro-op each on pipe FP1, one per cycle.

Forms

Every encoding of FUCOM that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FUCOM st(i)` FUCOM_ST0_X87	`DD E0+i`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(st0) or empty(src):
    underflow()
    x = 3                            # unordered
else:
    x = ucomi(st0, src)              # only an SNaN raises IE
c3 = x in (2, 3)                     # set with IE or DE unmasked too
c2 = x == 3
c0 = x in (1, 3)
c1 = 0

Run on AMD Zen 5 (EPYC 9645): 38 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FUCOM st(i)`
`st(i)`	explicit	read
`x87 status word`	implicit	write

Flags

M modified; blank: not affected. How to read.

C0	C1	C2	C3
All forms
M	M	M	M

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Without FUCOMI#

What Zen 5 did#