FUCOMI instruction (x87)

FUCOMI compares ST(0) with ST(i) and sets ZF, PF and CF the way FCOMI does: all clear when ST(0) is greater, CF for less, ZF for equal, all three for unordered. FCOMI’s page covers the flag pattern, the popping form FUCOMIP and what Zen 5 does differently from Intel’s manual. The one difference between the two is the U, for unordered: FUCOMI raises the invalid-operation exception only for a signaling NaN, where FCOMI raises it for any NaN.

Quiet and signaling compares

C draws the same line: its relational operators <, <=, > and >= raise the invalid exception for a NaN, while ==, != and the macros isless, isgreater and their kin compare quietly. GCC 14 at -O2 follows that for long double: a < b becomes FCOMIP, while isless(a, b) and a == b become FUCOMIP. Clang 23 uses FUCOMIP for all of them, so its a < b on a QNaN leaves IE clear.

An equality test has to look at two flags, since ZF alone is also set by an unordered result: GCC follows FUCOMIP with SETNP and a CMOVNE, Clang with SETNP, SETE and an AND. A NaN is the only value unordered with itself, so both compile __builtin_isnan(x) to fucomip st, st(0) and SETP.

What still raises IE

An SNaN in either register.
An unsupported encoding, such as an unnormal: Zen 5 raised IE for it as FCOMI does, and set all three flags.
An empty register, as a stack underflow: IE and SF, C1 = 0.

With IE unmasked, a QNaN still raised nothing on Zen 5: the flags said unordered and no #MF followed. A denormal raises DE.

FUCOMI came with the P6 family together with FCOMI and FCMOVB and its kin, reported by the CMOV bit of CPUID together with FPU. The x87’s older FUCOM makes the same distinction but reports in the condition codes. For floats and doubles in XMM registers, UCOMISS and UCOMISD are the quiet compares and COMISS the signaling one. AMD’s Zen 5 guide lists FUCOMI, like FCOMI, as two macro-ops.

Forms

Every encoding of FUCOMI that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FUCOMI ST(0), st(i)` FUCOMI_ST0_X87	`DB E8+i`	CMOV + FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(src1) or empty(src2):
    underflow()
    x = 3                            # unordered
else:
    x = ucomi(src1, src2)            # only an SNaN raises IE
zf = x in (2, 3)                     # set with IE or DE unmasked too
pf = x == 3
cf = x in (1, 3)
of = sf = af = 0                     # C0 to C3 are kept, C1 but after
                                     # a stack fault

Run on AMD Zen 5 (EPYC 9645): 25 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FUCOMI ST(0), st(i)`
`ST(0)`	explicit	read
`st(i)`	explicit	read
`x87 status word`	implicit	write
`RFLAGS`	implicit	write

Flags

M modified, 0 cleared; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF	C1
All forms
0	0	M	0	M	M	M

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`FCOMI` x87	CMOV + FPU `CPUID.01H:EDX[15]` CMOV `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Quiet and signaling compares#

What still raises IE#