FUCOMIP instruction (x87)

FUCOMIP is FUCOMI followed by a pop. It compares ST(0) with ST(i), sets ZF, PF and CF, raises the invalid-operation exception only for a signaling NaN or an unsupported encoding, and then marks ST(0) empty and increments TOP. The flag pattern is on FCOMI’s page and the quiet compare on FUCOMI’s; this page is about the pop. The encoding is DF E8+i, against FUCOMI’s DB E8+i.

The compare compilers emit

For long double, Clang 23 at -O2 compiles every comparison to FUCOMIP, and GCC 14 the equality tests and the quiet macros such as isless. Both operands arrive by FLD, so the pop fits: fucomip st, st(1) consumes the value loaded last, and fstp st(0) drops the other, leaving the stack as it was. Clang’s assembly output spells the mnemonic fucompi; GNU as 2.44 accepts both spellings and encodes either as DF E9 for ST(1).

When it pops

Exceptions masked: always. Zen 5 popped after a stack underflow too (an empty ST(i): IE, SF, C1 = 0, the flags unordered), and after a denormal operand, which raises DE and compares as its value.
IE unmasked: for an SNaN or an empty register, Zen 5 left TOP and the tags alone, still set ZF, PF and CF to unordered, and #MF came at the next waiting instruction. A handler that returns finds ST(0) still on the stack, so code that unmasks IE cannot count on the pop. The Operation section treats an unmasked DE for a denormal the same way.
fucomip st, st(0) compares ST(0) with itself and pops it: ZF for a number, all three flags for a NaN; Zen 5’s case with -2.5 set ZF.

C1 follows AMD’s manual: Zen 5 kept a C1 of 1 through an ordinary compare and cleared it only for the stack fault, where Intel’s manual clears it always.

The P6 family brought FUCOMIP with FCOMI and the other new compares; the CMOV bit of CPUID reports it, together with FPU. AMD’s Zen 5 guide lists FUCOMIP, like FUCOMI, as two macro-ops.

Forms

Every encoding of FUCOMIP that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FUCOMIP ST(0), st(i)` FUCOMIP_ST0_X87	`DF E8+i`	CMOV + FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(src1) or empty(src2):
    underflow()
    x = 3                            # unordered
else:
    x = ucomi(src1, src2)            # only an SNaN raises IE
zf = x in (2, 3)                     # set with IE or DE unmasked too
pf = x == 3
cf = x in (1, 3)
of = sf = af = 0                     # C0 to C3 are kept, C1 but after
                                     # a stack fault
pop()                                # not with IE or DE unmasked

Run on AMD Zen 5 (EPYC 9645): 11 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FUCOMIP ST(0), st(i)`
`ST(0)`	explicit	read
`st(i)`	explicit	read
`x87 register stack`	implicit	pop
`x87 status word`	implicit	write
`RFLAGS`	implicit	write

Flags

M modified, 0 cleared; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF	C1
All forms
0	0	M	0	M	M	M

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`FCOMI` x87	CMOV + FPU `CPUID.01H:EDX[15]` CMOV `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

The compare compilers emit#

When it pops#