FWAIT instruction (x87)

FWAIT, one byte, 9B, does nothing but check for a pending unmasked x87 exception: if the status word has ES set, it raises #MF, and otherwise execution goes on. WAIT is another name for the same opcode. Intel’s manual treats the x87 and the integer unit as separate units that run side by side, and FWAIT as the point where they synchronize.

Delayed exceptions

An x87 instruction that hits an unmasked exception does not fault itself. It sets the exception’s flag and ES, and the #MF comes at the next x87 instruction that waits, or at an FWAIT. Integer instructions may run in between, so a handler may find that the operand which caused the exception has already been overwritten in memory; Intel’s manual explains this and recommends a waiting instruction right after any x87 instruction whose memory operands matter, a store in particular. This site’s probe does that: every x87 case runs its instruction and then an FWAIT, which is where the #MF of an exception the instruction raised is recorded; a case that starts with one pending gets it at the instruction itself.

Zen 5’s own five cases follow the rule: with IE, UE or ZE flagged, unmasked and ES set, FWAIT raised #MF and changed nothing; with DE and PE flagged but masked, so ES clear, it ran through. Both manuals leave C0 to C3 undefined; Zen 5 kept them. SSE exceptions are not its business: MXCSR’s unmasked exceptions raise #XM at the instruction itself.

The waiting mnemonics

Most x87 control instructions come in two forms, and the one without N is the other with an FWAIT in front: GNU as 2.44 encodes fstsw ax as 9B DF E0, finit as 9B DB E3 and fstenv as 9B D9 /6. They are listed on the pages of the no-wait forms, such as FNSTSW, FNINIT and FNSTENV. GCC 14 and Clang 23 emit the no-wait forms and no FWAIT in the x87 code we built.

Other effects

FWAIT raises #NM only when CR0.MP and CR0.TS are both set, where the other x87 instructions raise it for EM or TS. With CR0.NE clear, AMD’s manual has a pending exception assert the FERR output and wait for an external interrupt instead of raising #MF.

AMD’s Zen 5 instruction table lists FWAIT twice: once as one macro-op, six per cycle, and once as microcoded.

Forms

Every encoding of FWAIT that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FWAIT` FWAIT	`9B`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

pass                                 # a pending exception raises #MF

Run on AMD Zen 5 (EPYC 9645): 5 cases.

Operands

None: XED lists no operands for this form.

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions