FXAM instruction (x87)

FXAM classifies ST(0) and reports the class in the condition codes C3, C2 and C0, and its sign in C1. It reads the register without changing it, raises no floating-point exception and works on an empty register too, so it is the x87’s way of asking what a value is before doing anything with it.

The classes

ST(0) is	C3	C2	C0
unsupported: an unnormal, pseudo-NaN or pseudo-infinity	0	0	0
a NaN, quiet or signaling	0	0	1
a normal finite number	0	1	0
an infinity	0	1	1
a zero	1	0	0
empty	1	0	1
a denormal, pseudo-denormals included	1	1	0

On Zen 5, every class came out as listed, the QNaN indefinite as a NaN and a pseudo-denormal (exponent 0 with the integer bit set) as a denormal. C1 is bit 79 even for an empty register, which still holds the bits of whatever was last there: two of Zen 5’s cases on empty registers gave C1 = 1 and C1 = 0.

After FNSTSW AX the bits sit in AH at bit 0 (C0), bit 2 (C2), bit 6 (C3) and bit 1 (C1), so a TEST of AH with 45H isolates the class.

From C

GCC 14 at -O2 compiles __builtin_signbit(x) on a long double to FLD, FXAM, fnstsw ax and and eax, 512, which keeps C1, bit 9 of the status word; Clang 23 reads bit 79 from the argument in memory instead. For isnan, isinf and fpclassify neither uses FXAM: they compare with FUCOMI, against the value itself and against the largest finite number, or Clang tests the bits in memory.

A waiting instruction

FXAM checks for a pending unmasked exception before it runs, as other x87 arithmetic does: a case of Zen 5 with IE set and unmasked in the status word raised #MF at FXAM and left the condition codes alone. Otherwise C0 to C3 are all written, and nothing else in the status word changes.

AMD’s Zen 5 guide lists FXAM as one macro-op on either of two FP pipes, two per cycle. FTST compares ST(0) with zero instead, and FCOM with another value.

Forms

Every encoding of FXAM that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FXAM` FXAM	`D9 E5`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(st0):                       # C3, C2, C0: the class of ST(0)
    k = 0b101
elif is_unsupported(st0):
    k = 0b000
elif is_nan(st0):
    k = 0b001
elif is_inf(st0):
    k = 0b011
elif is_zero(st0):
    k = 0b100
elif is_denormal(st0):
    k = 0b110                        # pseudo-denormals too
else:
    k = 0b010                        # a normal number
c3 = k >> 2
c2 = k >> 1 & 1
c0 = k & 1
c1 = st0 >> 79                       # the sign, of an empty register
                                     # too; FXAM raises nothing

Run on AMD Zen 5 (EPYC 9645): 30 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FXAM`
`ST(0)`	implicit	read, write
`x87 status word`	implicit	write

Flags

M modified; blank: not affected. How to read.

C0	C1	C2	C3
All forms
M	M	M	M

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

The classes#

From C#

A waiting instruction#