FXCH instruction (x87)

FXCH swaps ST(0) with another x87 register, ST(1) when no operand is given. x87 arithmetic always involves ST(0), and its results land on ST(0) or on the register the instruction names, so code that keeps several values on the stack uses FXCH to bring the next one to the top. Compilers emit it where the order of loads and operations does not fit the stack: GCC 14 at -O2 compiles a / b - b / a on long double to

two FLDs and an fld st(1) that copies a,
fdiv st, st(1) for a / b, then fxch st(1),
fdivrp st(2), st for b / a, and fsubrp st(1), st.

Clang 23 emits an FXCH there too, with the loads in the other order.

What it changes

Only the two registers trade places, with their contents and whether they are full; TOP and the other registers stay. C1 is cleared, and C0, C2 and C3 are undefined. If either register is empty, FXCH is a stack underflow; with IE masked, the empty one is replaced by the QNaN indefinite before the exchange, so both registers end up full.

What the guides say

Since every operation pivots on ST(0), x87 code spends instructions on moving values to the top. AMD’s Zen 5 guide advises using FXCH rather than a push and a pop to swap register values, as much faster (Section 2.11.3), and its instruction table lists FXCH as one macro-op that any of four pipes can run. Intel’s optimization manual counts the need for FXCH among the costs of x87 code that the flat registers of SSE2 avoid (Sections 3.9.4 and 7.3).

XED also decodes DD C8+i and DF C8+i as FXCH, two encodings it marks as undocumented; Zen 5 ran both as FXCH ST(i).

Forms

Every encoding of FXCH that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FXCH st(i)` FXCH_ST0_X87	`D9 C8+i`	FPU
`FXCH st(i)` undocumented FXCH_ST0_X87_DFC1	`DF C8+i`	FPU
`FXCH st(i)` undocumented FXCH_ST0_X87_DDC1	`DD C8+i`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(st0) or empty(src):
    underflow()
a = INDEFINITE if empty(st0) else st0
b = INDEFINITE if empty(src) else src.read()
src.write(a)                         # an empty one of the two gives
st0 = b                              # the indefinite
c1 = 0
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 18 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FXCH st(i)`
`st(i)`	explicit	read, write
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

What it changes#

What the guides say#