FXRSTOR

FXRSTOR loads the x87, MMX and SSE state back from the 512-byte area that FXSAVE writes, whose page describes the layout; FXRSTOR64 (REX.W) reads the x87 pointers as 64-bit offsets instead of 32-bit offsets with selectors. In 64-bit mode it loads XMM0 to XMM15 and MXCSR. Bytes 464 to 511 are left to software and ignored.

Faults#

• Alignment: the area must be aligned to 16 bytes. Zen 5 raised #GP for an address aligned only to 8.
• MXCSR: a bit set that MXCSR_MASK does not allow is #GP. Zen 5’s mask is 0002FFFFH: an image with bit 16 set faulted, and the mask allows bit 17, AMD’s mask for the misaligned-access exception, which no case loaded. Intel’s manual calls every bit from 16 up reserved.

Neither fault loaded anything on Zen 5.

What it does not check#

FXRSTOR is not a waiting instruction, and it loads the status word as it is, a pending exception included: Zen 5 loaded an image with IE flagged and unmasked, and the #MF came at the next waiting instruction, not at FXRSTOR. Intel’s manual suggests an FWAIT after FXRSTOR to raise such exceptions at a known point. MXCSR works the other way: a flag loaded with its exception unmasked raises nothing until that exception happens again, as both manuals say.

The tag word in the area has one bit per register, set when it is not empty, and FXRSTOR works out the full tags from the contents, as FRSTOR does.

The pointers: AMD’s manual and Zen 5#

AMD’s manual says that FXRSTOR loads the last instruction and data pointers and the opcode only when ES, worked out from the loaded flags and masks, is set, matching its FXSAVE, which stores them only then. Zen 5 loaded them regardless: from an image with ES clear, the opcode 123H and the data pointer were in place for the FNSAVE that followed, in both forms (the probe does not record the instruction pointer). Intel’s manual has them loaded every time.

From C, _fxrstor(p) and _fxrstor64(p) need -mfxsr; GCC 14 and Clang 23 at -O2 emit one FXRSTOR or FXRSTOR64. XRSTOR reads the same 512 bytes as the start of its area, followed by the state that came after SSE. AMD’s Zen 5 guide lists FXRSTOR as microcoded.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = mem.address
if a % 16:
    fault(GP, 0)
m = load(a + 24, 32)
if m & ~mxcsr_mask:                  # a bit MXCSR lacks
    fault(GP, 0)
sw = load(a + 2, 16)
t = sw >> 11 & 7                     # TOP from the area
for i in range(8):                   # ST(i) from that TOP
    v = load(a + 32 + 16 * i, 80)
    st[(t - top + i) % 8] = v
tags = load(a + 4, 8)
tw = 0
for j in range(8):                   # Rj empty where its bit is
    if not tags >> j & 1:            # clear; the others valid,
        tw |= 3 << 2 * j             # zero or special by what
ftw = tw                             # they hold
fcw = load(a, 16)
fsw = sw                             # an exception pending too
fop = load(a + 6, 16)                # 11 bits
fip = load(a + 8, 32)                # 32-bit offsets
fcs = load(a + 12, 16)
fdp = load(a + 16, 32)
fds = load(a + 20, 16)
mxcsr = m
for i in range(16):
    xmm[i] = load(a + 160 + 16 * i, 128)

a = mem.address
if a % 16:
    fault(GP, 0)
m = load(a + 24, 32)
if m & ~mxcsr_mask:                  # a bit MXCSR lacks
    fault(GP, 0)
sw = load(a + 2, 16)
t = sw >> 11 & 7                     # TOP from the area
for i in range(8):                   # ST(i) from that TOP
    v = load(a + 32 + 16 * i, 80)
    st[(t - top + i) % 8] = v
tags = load(a + 4, 8)
tw = 0
for j in range(8):                   # Rj empty where its bit is
    if not tags >> j & 1:            # clear; the others valid,
        tw |= 3 << 2 * j             # zero or special by what
ftw = tw                             # they hold
fcw = load(a, 16)
fsw = sw                             # an exception pending too
fop = load(a + 6, 16)                # 11 bits
fip = load(a + 8, 64)                # 64-bit offsets
fdp = load(a + 16, 64)
mxcsr = m
for i in range(16):
    xmm[i] = load(a + 160 + 16 * i, 128)

Operands

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms

aligned memory operand; may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to FXRSTOR, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More FXSR instructions

• FXSAVE