FXTRACT instruction (x87)

FXTRACT splits ST(0) into its exponent and its significand: the exponent, as an ordinary floating-point integer, replaces ST(0), and the significand, with the sign of the number and a magnitude from 1 to just under 2, is pushed on top of it. Zen 5 turned 10 into 1.25 in ST(0) over 3 in ST(1), and -0.1 into -1.6 over -4. Both parts are exact, so FXTRACT never sets PE. FSCALE is its inverse: it multiplies the significand by 2 to the power of the exponent.

From C

With -ffast-math, GCC 14 at -O2 compiles three functions on a long double to it:

logbl(x) to FXTRACT and fstp st(0), keeping the exponent;
significandl(x) to FXTRACT and fstp st(1), keeping the significand;
ilogbl(x) to logbl’s sequence and a truncating FISTP between two FLDCWs.

frexpl, whose significand runs from 0.5 to under 1, stays a call. Without that option, and with Clang 23 in either case, all of these are calls of the library.

The edges

Zero. FXTRACT of +0 or -0 is a division by zero: ZE, an exponent of -infinity and a significand of the zero’s own sign. With ZE unmasked, Zen 5 raised #MF and left the registers and TOP alone (C1 was cleared).
Infinity. An infinite significand of the same sign over an exponent of +infinity, without an exception.
Denormals. DE, and the result is normalized: Zen 5 gave 1 over -16445 for the smallest denormal, 2^-16445, and 1 over -16382 for the pseudo-denormal with the same value as 2^-16382. Neither manual says more about denormals than the DE.
NaNs and unsupported encodings. A QNaN lands in both registers; an SNaN raises IE and lands in both quieted. An unnormal or a pseudo-infinity raises IE, with the QNaN indefinite in both.

FXTRACT needs ST(7) empty for its push. With a full stack and IE masked, Zen 5 set IE and SF, ended with C1 set (it was set before too) and left the QNaN indefinite in both registers, the original value lost; an empty ST(0) did the same but cleared C1.

AMD’s Zen 5 guide lists FXTRACT as microcoded.

Forms

Every encoding of FXTRACT that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FXTRACT` FXTRACT	`D9 F4`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(st0):
    underflow()                  # IE, SF, C1 = 0
    st0 = INDEFINITE
    push(INDEFINITE)
elif not empty(st7):
    overflow()                   # the push has no room: IE, SF, C1 = 1
    st0 = INDEFINITE
    push(INDEFINITE)
else:
    e = exponent(st0)            # of a zero: -inf, with ZE
    s = significand(st0)         # 1 <= |s| < 2, the sign of ST(0)
    st0 = e                      # the exponent ends in ST(1)
    push(s)
    c1 = 0
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 25 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FXTRACT`
`ST(0)`	implicit	read, write
`ST(1)`	implicit	write
`x87 register stack`	implicit	push
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

From C#

The edges#