Instruction
FYL2X
Stores ST(1) times log2(ST(0)) in ST(1) and pops the register stack.
- Extensions
- Forms
- 1 (1 Legacy)
- Data
- Intel XED v2026.08.23
FYL2X computes y * log2(x), with x in ST(0) and y in ST(1): it stores the product in ST(1) and pops, so the result ends up in ST(0). The factor y is what makes it useful. The x87 has only the binary logarithm, and the others follow from it by a constant that a load instruction pushes first:
- the natural logarithm: FLDLN2, x, FYL2X, since ln(x) = ln(2) * log2(x);
- the common logarithm: FLDLG2 instead, log10(2);
- log2(x) itself: FLD1.
The product is rounded once, so only the constant has been rounded before it. For x close to 1, where x - 1 has lost bits by the time FYL2X sees x, FYL2XP1 takes x - 1 instead.
The edges
- x = 0 of either sign is a division by zero: ZE, and y times -infinity. Zen 5 gave -infinity for y = 1, and +infinity for y = -2.5 and x = -0.
- A negative x, -infinity included, is an invalid operation: IE, and with it masked the QNaN indefinite. So are the products of a zero and an infinity: y = 0 with x = 0 or +infinity, and an infinite y with x = 1. An infinite y with x = 0 gives an infinity without ZE.
- log2(1) is an exact +0 for y = 2. Other exact results still raise PE on Zen 5: log2(8) * 3 gave 9, and log2(0.5) * -1 gave 1, both with PE.
- A denormal x sets DE: the smallest, 2^-16445, gave -16445.
- The largest x times the largest y overflows: OE.
For ordinary operands the page’s pseudocode checks Zen 5’s results within 1 ulp (1.5 when not rounding to nearest), and the worst of its 20 recorded results was 0.42 ulp to nearest and 0.94 in the other modes.
From C
GCC 14 and Clang 23 at -O2 compile logl, log2l and log10l on a
long double to calls of the library. With -ffast-math, GCC emits the
three sequences above, a constant, an fld of x and fyl2x; Clang 23
still calls the library.
AMD’s Zen 5 guide lists FYL2X as microcoded, and Intel’s optimization manual suggests software implementations where 80 bits are not needed (Section 3.9.1).
Forms
| Instruction | Encoding | Requires |
|---|---|---|
FYL2X
FYL2X | D9 F1 | FPU |
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
x = st0
y = st1
if empty(st0) or empty(st1):
underflow() # IE, SF, C1 = 0
st1 = INDEFINITE
else:
st1 = ylog2(y, x) # y * log2(x), rounded once, within
# 1 ulp (1.5 when not rounding to
# nearest); Zen 5's 20 recorded
# results: 0.42 at most to nearest,
# 0.94 in the other modes. x = 0
# raises ZE; x < 0, 0 *
# log2(0), inf * log2(1) and 0 * inf
# raise IE
pop() # the result is ST(0) now
c0 = c2 = c3 = UNDEFINED # Zen 5 keeps them
Run on AMD Zen 5 (EPYC 9645): 52 cases.
Operands
| Operand | Kind | Action |
|---|---|---|
FYL2X | ||
ST(0) | implicit | read |
ST(1) | implicit | read, write |
x87 register stack | implicit | pop |
x87 status word | implicit | write |
Flags
| C0 | C1 | C2 | C3 |
|---|---|---|---|
| All forms | |||
| U | M | U | U |
Attributes
What else XED records about the forms. How to read.
- All forms
- may abort a TSX transaction
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
X87 | FPU | Every x86-64 processor in XED’s model and Zen 3 to Zen 6 |
More x87 instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s
-marchfeature sets and AMD’s Processor Programming References, which the page of each processor cites. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-422 (FYL2X)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
- AMD64 Architecture Programmer's Manual, Volume 5: 64-Bit Media and x87 Floating-Point Instructions (26569, rev. 3.16, November 2021), Wayback Machine copy of AMD's PDF
- Intel 64 and IA-32 Architectures Optimization Reference Manual, Volume 1 (248966-051, October 2026)
- Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.