FYL2XP1 instruction (x87)

FYL2XP1 computes y * log2(x + 1), with x in ST(0) and y in ST(1): it stores the product in ST(1) and pops, so the result ends up in ST(0). It is FYL2X for an argument close to 1, given as its distance x from 1. Adding 1 to a small x in a register drops the low bits of x, and no logarithm of the sum can bring them back; FYL2XP1 never forms the sum: for x = -2.6 * 10^-14, Zen 5’s result was within 0.28 ulp of the exact product, rounding to nearest. With FLDLN2 as y the result is ln(1 + x), C’s log1p.

In log1pl

With -ffast-math, GCC 14 at -O2 compiles log1pl(x) on a long double to FLDLN2 and a test of |x| against 1 - sqrt(2)/2, about 0.2929, held as an 80-bit constant: below it FYL2XP1 on x, otherwise FLD1, FADDP and FYL2X on 1 + x. Clang 23 calls the library’s log1pl.

The range, in the manuals and on Zen 5

Intel’s manual allows |x| < 1 - sqrt(2)/2, the bound GCC tests, and leaves the result undefined outside it, exceptions included. AMD’s manual gives sqrt(1/2) - 1 to sqrt(2) - 1: the same lower end, but up to about 0.4142. Zen 5 went beyond both:

With y = 1, x = 0.9, x = 3 and the largest finite x gave results within 0.13 ulp of log2(1 + x); x = -(1 - 2^-64), just above -1, gave exactly -64.
For x of -1 or below, where log2(1 + x) is -infinity or no number, it returned x itself with PE and without ZE or IE: -1 for x = -1, -2 for x = -2, with each finite, nonzero y tried.

Other edges

A zero times an infinity is an invalid operation (IE): x = 0 with an infinite y, x = +infinity with y = 0; so is x = -infinity.
An exact result still sets PE: x = 1 with y = 2 gave 2, and x = 3 with y = 1 gave 2.
A denormal operand sets DE; the smallest denormal x with y = 1 gave the same denormal back, with UE and PE.

AMD’s Zen 5 guide lists FYL2XP1 as microcoded.

Forms

Every encoding of FYL2XP1 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FYL2XP1` FYL2XP1	`D9 F9`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = st0
y = st1
if empty(st0) or empty(st1):
    underflow()                  # IE, SF, C1 = 0
    st1 = INDEFINITE
elif is_finite(x) and not less(-1, x):
    if is_finite(y) and not is_zero(y):
        if is_denormal(y):
            de = 1
        st1 = x                  # x <= -1: log2(x + 1) is no
        pe = 1                   # number; Zen 5 gives x, inexact
        c1 = 0
    else:
        st1 = ylog2p1(y, x)      # y 0 or infinite: a signed 0 or
                                 # infinity; else a NaN or IE
else:
    st1 = ylog2p1(y, x)          # y * log2(x + 1), rounded once:
                                 # within 1 ulp (1.5 when not
                                 # rounding to nearest); Zen 5's 26
                                 # recorded results: 0.47 at most to
                                 # nearest, 0.72 in the other modes.
                                 # The manuals give |x| < 1 -
                                 # sqrt(2)/2; the 9 of them outside
                                 # it (x from -1 + 2^-64 to 3, and
                                 # the largest number) are as close
pop()
c0 = c2 = c3 = UNDEFINED         # Zen 5 keeps them

Run on AMD Zen 5 (EPYC 9645): 62 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FYL2XP1`
`ST(0)`	implicit	read
`ST(1)`	implicit	read, write
`x87 register stack`	implicit	pop
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

In log1pl#

The range, in the manuals and on Zen 5#

Other edges#