Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of GETSEC that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
GETSEC GETSECNP 0F 37SMX

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cr4 >> 14 & 1:
    fault(UD)                    # CR4.SMXE clear (and on AMD's
                                 # processors, which have no SMX)
if vmx_nonroot:
    vm_exit(11)                  # the hypervisor emulates it
n = eax                          # the leaf
caps = smx_capabilities(0)       # bits 8:2: the leaves 2 to 8
if n > 30 or n and not caps >> n & 1:
    fault(UD)                    # a leaf the processor lacks
if n == 0:
    eax = smx_capabilities(ebx)  # CAPABILITIES, at any CPL: bit 0
                                 # a TXT chipset; bit 31, more at
                                 # the next EBX
elif n == 6:
    leaf_function(n)             # PARAMETERS, at any CPL: the
                                 # parameter EBX selects, in EAX,
                                 # EBX and ECX
elif CPL > 0:
    fault(GP, 0)
else:
    leaf_function(n)             # ENTERACCS (2), EXITAC (3), SENTER
                                 # (4), SEXIT (5), SMCTRL (7) and
                                 # WAKEUP (8), each with checks of
                                 # its own (#GP(0)) on its page

Run on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no SMX, and every one raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
GETSEC
EAXimplicitread, conditional write
EBXimplicitread

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms
not in real-address mode; may abort a TSX transaction

Leaf functions

GETSEC performs the leaf function whose number is in EAX; each has a page of its own. GETSEC[CAPABILITIES] reports which leaves the processor supports, and leaf 1 is reserved. tboot defines every other number but EXITAC, which only authenticated code modules run; its number is the one the manual gives.

EAXLeaf functionSummary
00HGETSEC[CAPABILITIES]Returns a bit for each GETSEC leaf the processor supports and one for an Intel TXT chipset; any privilege level may run it.
02HGETSEC[ENTERACCS]Loads the authenticated code module at the physical address in EBX, checks its signature with the chipset's key and runs it.
03HGETSEC[EXITAC]Leaves authenticated code execution mode and continues at the address in EBX; an authenticated code module ends with it.
04HGETSEC[SENTER]Launches a measured environment: authenticates the module at the physical address in EBX and gathers the other logical processors.
05HGETSEC[SEXIT]Ends the measured environment that SENTER launched, signalling every logical processor of the platform.
06HGETSEC[PARAMETERS]Returns one SMX parameter per index in EBX, such as the versions of authenticated code modules that the processor accepts.
07HGETSEC[SMCTRL]Performs the SMX mode control that EBX selects; the only one, 0, unmasks SMIs after a measured launch.
08HGETSEC[WAKEUP]Wakes the other logical processors from the sleep state that the SENTER rendezvous left them in, so that they join the measured environment.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
SMX

SMX
CPUID.01H:ECX[6] SMX

Core (Merom, Conroe), Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill

Note: XED's AMD chips, which it derives from its Intel chips, have SMX too; AMD processors do not implement GETSEC, so this list leaves them out.

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
  3. tboot 1.12.2: tboot/include/txt/smx.h (GETSEC leaf numbers, BSD license)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.