GF2P8MULB instruction (GFNI)

In the optimization guide

What the optimization guide says about GF2P8MULB, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Tremont

Vectors and cryptography: Tremont adds the Galois-field instructions, for ciphers, error correction and bit-matrix multiplication, which run on port 20, and speeds up pclmulqdq; Intel gives no numbers.

Forms

Every encoding of GF2P8MULB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`GF2P8MULB xmm, xmm` GF2P8MULB_XMMu8_XMMu8	`66 0F 38 CF /r`	GFNI
`GF2P8MULB xmm, m128` GF2P8MULB_XMMu8_MEMu8	`66 0F 38 CF /r`	GFNI

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each byte of the result comes from the byte in the same place in each source.

Shown: bytes 7 to 0. Every byte works alike: 16 bytes in the xmm form.

Result byte i comes from byte i of xmm1 and xmm2. Result bytes 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(16):
    a = xmm1.b[i]
    b = src2.b[i]
    xmm1.b[i] = gf2p8mul(a, b)
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`GF2P8MULB xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to GF2P8MULB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_gf2p8mul_epi8` `__m128i _mm_gf2p8mul_epi8(__m128i __A, __m128i __B)`	`GF2P8MULB xmm, xmm` Legacy -mgfni

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`GFNI` GFNI	GFNI `CPUID.(EAX=07H,ECX=0):ECX[8]` GFNI	Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Zen 4, Zen 5, Zen 6

GF2P8MULB