HADDPD

HADDPD adds the two doubles of each operand: the low result is the sum of the first operand’s pair and the high result that of the second’s, so haddpd xmm0, xmm1 gives xmm0[0] + xmm0[1] below and xmm1[0] + xmm1[1] above. The sums round under MXCSR as ADDPD’s do. HSUBPD subtracts the high double of each pair from the low one, HADDPS adds pairs of singles, PHADDD pairs of integers, and VHADDPD is the VEX form, which works within each 128-bit lane. HADDPD is SSE3, beyond the first x86-64 level; as a legacy SSE instruction it keeps bits 128 and up (see SSE and AVX) and needs a memory operand aligned to 16 bytes.

The low element of each pair is the first operand of its addition, which decides the result when both are NaNs. On Zen 5, haddpd xmm8, xmm15, with a quiet NaN below a signaling one in XMM8, returned the quiet NaN unchanged, and the signaling NaN of XMM15 plus 1.0 gave it made quiet; IE was set. With DAZ set, haddpd xmm1, xmmword ptr [mem] counted the denormal inputs as zero, so each pair summed to the smallest normal double, and no flag was set.

Not the usual reduction#

Our compilers avoid HADDPD for sums of a whole vector. In our builds at -O2 with -march=x86-64-v2, v[0] + v[1] on a __m128d is UNPCKHPD and ADDSD in both GCC 14 and Clang 23, and a sum over an array with -ffast-math ends the same way in Clang. _mm_hadd_pd compiles to HADDPD, Clang also uses it with -Os for v[0] + v[1], and for r[i] = a[2*i] + a[2*i+1], a sum of adjacent pairs, Clang vectorizes with one HADDPD per two results while GCC keeps the loop scalar.

AMD’s latency spreadsheet for Zen 5 lists HADDPD as several macro-ops, with a latency of 4 cycles and one started every two cycles, where ADDPD is one macro-op with a latency of 2 cycles and two per cycle.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

src1 = xmm1.read()  # xmm1 as it was
for i in range(2):
    j = 2 * (i % 1)
    if i < 1:
        a = src1.f64[j]
        b = src1.f64[j + 1]
        xmm1.f64[i] = add(a, b)
    else:
        a = src2.f64[j]
        b = src2.f64[j + 1]
        xmm1.f64[i] = add(a, b)
# bits 128 and up of the register are unchanged

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

Memory forms

aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to HADDPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSE3 instructions

• ADDSUBPD
• ADDSUBPS
• FISTTP
• HADDPS
• HSUBPD
• HSUBPS
• LDDQU
• MOVDDUP
• MOVSHDUP
• MOVSLDUP