HADDPS

HADDPS adds adjacent pairs of singles. From (a0, a1, a2, a3) in its first operand and (b0, b1, b2, b3) in its second it makes (a0 + a1, a2 + a3, b0 + b1, b2 + b3), each sum rounded under MXCSR as ADDPS rounds. HADDPD explains the pairing and which NaN wins for doubles, HSUBPS subtracts within the pairs, and VHADDPS works within each 128-bit lane. HADDPS came with SSE3, part of x86-64-v2; as a legacy SSE instruction it keeps bits 128 and up of the register (see SSE and AVX) and needs a memory operand aligned to 16 bytes.

Zen 5’s recorded cases: haddps xmm4, xmm4, holding the smallest denormal, the smallest normal, -2^-127 and the largest single, gave 2^-126 + 2^-149 exactly and the largest single, each twice, and set DE for the denormal inputs and PE for the rounded sum. With MXCSR at FFC0H (round toward zero, FTZ and DAZ set), -0 plus +0 from memory gave +0, as every rounding but downward does, and infinity plus 3 gave infinity.

Pairs, not totals#

In our builds at -O2 with -march=x86-64-v2, Clang 23 vectorizes r[i] = a[2*i] + a[2*i+1] with one HADDPS per four results, the second operand read from memory; GCC 14 separates the even and odd elements with two SHUFPS, 88h and DDh, and adds them with ADDPS. Neither uses it to total a vector: v[0] + v[1] + v[2] + v[3] keeps C’s order with ADDSS, and with -ffast-math both reduce with a half move, MOVHLPS in GCC and UNPCKHPD in Clang, and ADDPS. _mm_hadd_ps compiles to HADDPS as written.

Intel’s optimization manual compares dot products of four singles written with SSE alone, with HADDPS and with DPPS: on the Intel Core microarchitecture the HADDPS version had the higher throughput but was slightly slower because of its latency, and on the Enhanced Intel Core microarchitecture DPPS beat both (Section 7.6.1). AMD’s spreadsheet for Zen 5 lists HADDPS as four macro-ops with a latency of 4 cycles, one every two cycles, against one macro-op and 2 cycles for ADDPS.

In the optimization guide

What the optimization guide says about HADDPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Horizontal operations and reductions: HADDPS and VHADDPS are microcode or several macro-ops on AMD’s cores, and LLVM uses them only for Jaguar.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

src1 = xmm1.read()  # xmm1 as it was
for i in range(4):
    j = 2 * (i % 2)
    if i < 2:
        a = src1.f32[j]
        b = src1.f32[j + 1]
        xmm1.f32[i] = add(a, b)
    else:
        a = src2.f32[j]
        b = src2.f32[j + 1]
        xmm1.f32[i] = add(a, b)
# bits 128 and up of the register are unchanged

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

Memory forms

aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to HADDPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSE3 instructions

• ADDSUBPD
• ADDSUBPS
• FISTTP
• HADDPD
• HSUBPD
• HSUBPS
• LDDQU
• MOVDDUP
• MOVSHDUP
• MOVSLDUP